diff --git a/src/main/scala/Fetch.scala b/src/main/scala/Fetch.scala
index 5128b7d..04ce118 100644
--- a/src/main/scala/Fetch.scala
+++ b/src/main/scala/Fetch.scala
@@ -8,7 +8,6 @@ class Fetch(val bits: Int, val words: Int) extends Module {
     val mem = new MemoryPort(bits, words, false)
   })
 
-  io.mem.readEnable := true.B
   io.mem.addr := io.nia >> log2Ceil(bits/8)
 
   /* Issues with conditional entries in ports */
diff --git a/src/main/scala/LoadStore.scala b/src/main/scala/LoadStore.scala
index 34033c0..d0c3583 100644
--- a/src/main/scala/LoadStore.scala
+++ b/src/main/scala/LoadStore.scala
@@ -44,7 +44,6 @@ class LoadStore(val bits: Int, val words: Int) extends Module {
   io.out.bits := 0.U
 
   io.mem.addr := 0.U
-  io.mem.readEnable := false.B
   io.mem.writeMask := 0.U
   io.mem.writeData := 0.U
   io.mem.writeEnable := false.B
@@ -132,7 +131,6 @@ class LoadStore(val bits: Int, val words: Int) extends Module {
         state := sIdle
       } .otherwise {
         io.mem.addr := addr >> log2Ceil(bits/8).U
-        io.mem.readEnable := true.B
         state := sLoadFormat
       }
     }
@@ -194,7 +192,6 @@ class LoadStoreWrapper(val bits: Int, val size: Int, filename: String) extends M
 
   /* Fetch port is unused */
   mem.io.fetchPort.writeData := 0.U
-  mem.io.fetchPort.readEnable := false.B
   mem.io.fetchPort.writeEnable := false.B
   mem.io.fetchPort.addr := 0.U
   mem.io.fetchPort.writeMask := 0.U
diff --git a/src/main/scala/MemoryBlackBox.scala b/src/main/scala/MemoryBlackBox.scala
index 50cc148..7fd0b65 100644
--- a/src/main/scala/MemoryBlackBox.scala
+++ b/src/main/scala/MemoryBlackBox.scala
@@ -5,14 +5,12 @@ class MemoryBlackBox(val bits: Int, val words: Int, val filename: String) extend
   val io = IO(new Bundle() {
     val clock      = Input(Clock())
 
-    val readEnable1  = Input(Bool())
     val writeEnable1 = Input(Bool())
     val writeMask1   = Input(UInt((bits/8).W))
     val addr1        = Input(UInt(log2Ceil(words).W))
     val readData1    = Output(UInt(bits.W))
     val writeData1   = Input(UInt(bits.W))
 
-    val readEnable2 = Input(Bool())
     val readAddr2   = Input(UInt(log2Ceil(words).W))
     val readData2   = Output(UInt(bits.W))
   })
@@ -25,14 +23,12 @@ class MemoryBlackBox(val bits: Int, val words: Int, val filename: String) extend
       |) (
       |    input clock,
       |
-      |    input readEnable1,
       |    input writeEnable1,
       |    input [BITS/8-1:0] writeMask1,
       |    input [$$clog2(WORDS)-1:0] addr1,
       |    output reg [BITS-1:0] readData1,
       |    input [BITS-1:0] writeData1,
       |
-      |    input readEnable2,
       |    input [$$clog2(WORDS)-1:0] readAddr2,
       |    output reg [BITS-1:0] readData2
       |);
@@ -42,6 +38,8 @@ class MemoryBlackBox(val bits: Int, val words: Int, val filename: String) extend
       |
       |always@(posedge clock)
       |begin
+      |    readData1 <= ram[addr1];
+      |    readData2 <= ram[readAddr2];
       |    if (writeEnable1)
       |    begin
       |      for (i = 0; i < BITS/8; i = i + 1)
@@ -49,12 +47,6 @@ class MemoryBlackBox(val bits: Int, val words: Int, val filename: String) extend
       |        if (writeMask1[i]) ram[addr1][i*8+:8] <= writeData1[i*8+:8];
       |      end
       |    end
-      |    else if (readEnable1)
-      |    begin
-      |       readData1 <= ram[addr1];
-      |    end
-      |
-      |    if (readEnable2) readData2 <= ram[readAddr2];
       |end
       |initial begin
       |    $$readmemh("$filename", ram);
@@ -65,7 +57,6 @@ class MemoryBlackBox(val bits: Int, val words: Int, val filename: String) extend
 
 class MemoryPort(val bits: Int, val words: Int, val rw: Boolean) extends Bundle {
   val addr        = Output(UInt(log2Ceil(words).W))
-  val readEnable  = Output(Bool())
   val readData    = Input(UInt(bits.W))
 
   //val writeEnable = if (rw) Some(Output(Bool())) else None
@@ -86,14 +77,12 @@ class MemoryBlackBoxWrapper(val bits: Int, val words: Int, val filename: String)
 
   m.io.clock := clock
 
-  m.io.readEnable1 := io.loadStorePort.readEnable
   m.io.writeEnable1 := io.loadStorePort.writeEnable
   m.io.writeMask1 := io.loadStorePort.writeMask
   m.io.addr1 := io.loadStorePort.addr
   io.loadStorePort.readData := m.io.readData1
   m.io.writeData1 := io.loadStorePort.writeData
 
-  m.io.readEnable2 := io.fetchPort.readEnable
   m.io.readAddr2 := io.fetchPort.addr
   io.fetchPort.readData := m.io.readData2
 }
diff --git a/src/test/scala/MemoryBlackBox.scala b/src/test/scala/MemoryBlackBox.scala
index 9c71d81..f0f9861 100644
--- a/src/test/scala/MemoryBlackBox.scala
+++ b/src/test/scala/MemoryBlackBox.scala
@@ -19,11 +19,9 @@ class MemoryBlackBoxUnitTester extends FlatSpec with ChiselScalatestTester with
   behavior of "MemoryBlackBox"
   it should "pass a unit test" in {
     test(new MemoryBlackBoxWrapper(bits, words, filename)).withAnnotations(Seq(VerilatorBackendAnnotation, WriteVcdAnnotation, ClockInfoAnnotation(Seq(ClockInfo(period = 2))))) { m =>
-      m.io.fetchPort.readEnable.poke(true.B)
 
       m.io.fetchPort.addr.poke(0.U)
 
-      m.io.fetchPort.readEnable.expect(true.B)
       m.clock.step()
       m.io.fetchPort.readData.expect("h0001020304050607".U)