From 4ebe7adf28cde019b2ea30d4f40ba0d42d833896 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Thu, 6 Feb 2020 21:50:23 +1100 Subject: [PATCH] Buffer divide final formatting Add an extra cycle to the divider that buffers the final formatting. Signed-off-by: Anton Blanchard --- src/main/scala/SimpleDivider.scala | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/main/scala/SimpleDivider.scala b/src/main/scala/SimpleDivider.scala index d394aa0..ac53361 100644 --- a/src/main/scala/SimpleDivider.scala +++ b/src/main/scala/SimpleDivider.scala @@ -71,14 +71,15 @@ class SimpleDivider(val bits: Int) extends Module { overflow := quotient(63, 31).orR } - io.out.bits := quotient + val result = WireDefault(quotient) when (overflow) { - io.out.bits := 0.U + result := 0.U } .elsewhen (is32bit && !modulus) { - io.out.bits := 0.U(32.W) ## quotient(31, 0) + result := 0.U(32.W) ## quotient(31, 0) } - io.out.valid := (count === (bits+1).U) && busy + io.out.bits := RegNext(result) + io.out.valid := RegNext((count === (bits+1).U) && busy) when (io.out.valid) { busy := false.B }