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Remove SystemVerilog syntax

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Lattice Diamond doesn't seem to support SystemVerilog which is a bit
depressing. We only use the syntax in a few places, so fix that up.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This commit is contained in:
Anton Blanchard
2020-01-31 02:49:26 +11:00
committed by Anton Blanchard
parent 1aeb5dad28
commit 63ed617cb6
2 changed files with 7 additions and 7 deletions
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8
src/main/scala/MemoryBlackBox.scala
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@@ -29,18 +29,18 @@ class MemoryBlackBox(val bits: Int, val words: Int, val filename: String) extend
| input writeEnable1,
| input [BITS/8-1:0] writeMask1,
| input [$$clog2(WORDS)-1:0] addr1,
| output logic [BITS-1:0] readData1,
| output reg [BITS-1:0] readData1,
| input [BITS-1:0] writeData1,
|
| input readEnable2,
| input [$$clog2(WORDS)-1:0] readAddr2,
| output logic [BITS-1:0] readData2
| output reg [BITS-1:0] readData2
|);
|
|integer i;
|logic [BITS-1:0] ram[0:WORDS-1];
|reg [BITS-1:0] ram[0:WORDS-1];
|
|always_ff@(posedge clock)
|always@(posedge clock)
|begin
| if (writeEnable1)
| begin