From 2c44cd8bcee4317d569e1f1550b5128b28803ffd Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Mon, 22 Feb 2021 13:52:01 +1030 Subject: [PATCH 1/2] Add syscon regsiters to the loadstore unit This adds a really simple syscon so the potato uart in micropython can operate. Signed-off-by: Joel Stanley --- src/main/scala/LoadStore.scala | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/main/scala/LoadStore.scala b/src/main/scala/LoadStore.scala index 96a05ad..33d5c10 100644 --- a/src/main/scala/LoadStore.scala +++ b/src/main/scala/LoadStore.scala @@ -150,6 +150,26 @@ class LoadStore(val bits: Int, val words: Int) extends Module { data := d.zeroExtend(length) } + /* Syscon */ + when (addr(31, 8) === "hc00000".U) { + when (addr(7, 0) === "h00".U) { + /* SYS_REG_SIGNATURE */ + data := "hf00daa5500010001".U + } + when (addr(7, 0) === "h08".U) { + /* + * SYS_REG_INFO + * SYS_REG_INFO_HAS_UART is true + * Other bits are false + */ + data := "h1".U + } + when (addr(7, 0) === "h20".U) { + /* SYS_REG_CLKINFO */ + data := 50000000.U + } + } + /* UART */ when (addr(31, 8) === "hc00020".U) { when (addr(7, 0) === "h08".U) { From 21cdff79764efe4048ca1e88733defcf067a95af Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Mon, 22 Feb 2021 16:33:04 +1100 Subject: [PATCH 2/2] Make clock frequency settable at the top level of Core Rather than hardwiring LoadStore. Signed-off-by: Michael Neuling Signed-off-by: Joel Stanley --- src/main/scala/Core.scala | 6 +++--- src/main/scala/LoadStore.scala | 10 +++++----- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/main/scala/Core.scala b/src/main/scala/Core.scala index 8f24571..dc98a7b 100644 --- a/src/main/scala/Core.scala +++ b/src/main/scala/Core.scala @@ -6,7 +6,7 @@ import Control._ import Helpers._ import InstructionHelpers._ -class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int) extends Module { +class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int, clockFreq: Int) extends Module { val io = IO(new Bundle { val tx = Output(UInt(1.W)) val rx = Input(UInt(1.W)) @@ -40,7 +40,7 @@ class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int) extends val multiplier = Module(new SimpleMultiplier(bits)) val divider = Module(new SimpleDivider(bits)) val mem = Module(new MemoryBlackBoxWrapper(bits, memWords, memFileName)) - val loadStore = Module(new LoadStore(bits, memWords)) + val loadStore = Module(new LoadStore(bits, memWords, clockFreq)) val control = Module(new Control(bits)) val regFile = Module(new RegisterFile(32, bits, 3, 1, false)) @@ -445,5 +445,5 @@ class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int) extends } object CoreObj extends App { - (new ChiselStage).emitVerilog(new Core(64, 384*1024, "insns.hex", 0x0)) + (new ChiselStage).emitVerilog(new Core(64, 384*1024, "insns.hex", 0x0, 50000000)) } diff --git a/src/main/scala/LoadStore.scala b/src/main/scala/LoadStore.scala index 33d5c10..0c4dc39 100644 --- a/src/main/scala/LoadStore.scala +++ b/src/main/scala/LoadStore.scala @@ -32,7 +32,7 @@ class LoadStoreInput(val bits: Int) extends Bundle { * 2C: form store mask, store data */ -class LoadStore(val bits: Int, val words: Int) extends Module { +class LoadStore(val bits: Int, val words: Int, val clockFreq: Int) extends Module { val io = IO(new Bundle { val in = Flipped(Valid(new LoadStoreInput(bits))) val out = Output(Valid(UInt(bits.W))) @@ -166,7 +166,7 @@ class LoadStore(val bits: Int, val words: Int) extends Module { } when (addr(7, 0) === "h20".U) { /* SYS_REG_CLKINFO */ - data := 50000000.U + data := clockFreq.asUInt(bits.W) } } @@ -203,13 +203,13 @@ class LoadStore(val bits: Int, val words: Int) extends Module { } } -class LoadStoreWrapper(val bits: Int, val size: Int, filename: String) extends Module { +class LoadStoreWrapper(val bits: Int, val size: Int, val clockFreq: Int, filename: String) extends Module { val io = IO(new Bundle { val in = Flipped(Valid(new LoadStoreInput(bits))) val out = Output(Valid(UInt(bits.W))) }) - val loadStore = Module(new LoadStore(bits, size/(bits/8))) + val loadStore = Module(new LoadStore(bits, size/(bits/8), clockFreq)) val mem = Module(new MemoryBlackBoxWrapper(bits, size/(bits/8), filename)) io.in <> loadStore.io.in @@ -226,5 +226,5 @@ class LoadStoreWrapper(val bits: Int, val size: Int, filename: String) extends M } object LoadStoreObj extends App { - (new ChiselStage).emitVerilog(new LoadStoreWrapper(64, 128*1024, "test.hex")) + (new ChiselStage).emitVerilog(new LoadStoreWrapper(64, 128*1024, 50000000, "test.hex")) }