diff --git a/chiselwatt.core b/chiselwatt.core
index edcafb3..8b9edb9 100644
--- a/chiselwatt.core
+++ b/chiselwatt.core
@@ -16,6 +16,11 @@ filesets:
       - constraints/cmod_a7-35.xdc : {file_type : xdc}
       - pll/pll_mmcme2.v : {file_type : verilogSource}
 
+  arty_a7:
+    files:
+      - constraints/arty_a7.xdc : {file_type : xdc}
+      - pll/pll_bypass.v : {file_type : verilogSource}
+
   ecp5-evn:
     files:
       - constraints/ecp5-evn.lpf : {file_type : LPF}
@@ -31,6 +36,20 @@ targets:
       vivado: {part : xc7a35tcpg236-1}
     toplevel : toplevel
 
+  arty_a7-35:
+    default_tool: vivado
+    filesets: [core, arty_a7]
+    tools:
+      vivado: {part : xc7a35ticsg324-1L}
+    toplevel : toplevel
+
+  arty_a7-100:
+    default_tool: vivado
+    filesets: [core, arty_a7]
+    tools:
+      vivado: {part : xc7a100ticsg324-1L}
+    toplevel : toplevel
+
   ecp5-evn:
     default_tool: diamond
     filesets: [core, ecp5-evn]
diff --git a/constraints/arty_a7.xdc b/constraints/arty_a7.xdc
new file mode 100644
index 0000000..f442b0a
--- /dev/null
+++ b/constraints/arty_a7.xdc
@@ -0,0 +1,19 @@
+set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { clock }];
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { clock }];
+
+set_property -dict { PACKAGE_PIN C2    IOSTANDARD LVCMOS33 } [get_ports { reset }];
+
+set_property -dict { PACKAGE_PIN D10   IOSTANDARD LVCMOS33 } [get_ports { io_tx }];
+set_property -dict { PACKAGE_PIN A9    IOSTANDARD LVCMOS33 } [get_ports { io_rx }];
+
+set_property -dict { PACKAGE_PIN H5    IOSTANDARD LVCMOS33 } [get_ports { io_terminate }];
+
+set_property -dict { PACKAGE_PIN J5    IOSTANDARD LVCMOS33 } [get_ports { io_ledB }];
+set_property -dict { PACKAGE_PIN T9    IOSTANDARD LVCMOS33 } [get_ports { io_ledC }];
+
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
+
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
+set_property CONFIG_MODE SPIx4 [current_design]
diff --git a/constraints/cmod_a7-35.xdc b/constraints/cmod_a7-35.xdc
index 1048145..37b38f6 100644
--- a/constraints/cmod_a7-35.xdc
+++ b/constraints/cmod_a7-35.xdc
@@ -1,12 +1,12 @@
 ## Clock signal 12 MHz
 set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports { clock }];
-create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {clock}];
-
-set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { io_tx }];
-set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { io_rx  }];
+create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports { clock }];
 
 set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports { reset }];
 
+set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { io_tx }];
+set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { io_rx }];
+
 set_property -dict { PACKAGE_PIN A17   IOSTANDARD LVCMOS33 } [get_ports { io_terminate }];
 
 set_property -dict { PACKAGE_PIN C16   IOSTANDARD LVCMOS33 } [get_ports { io_ledB }];
diff --git a/openocd/digilent-hs1.cfg b/openocd/digilent-hs1.cfg
new file mode 100644
index 0000000..cfb16a0
--- /dev/null
+++ b/openocd/digilent-hs1.cfg
@@ -0,0 +1,14 @@
+# this supports JTAG-HS1 and JTAG-SMT1
+# (the later being the OEM on-board version)
+
+interface ftdi
+ftdi_device_desc "Digilent USB Device"
+ftdi_vid_pid 0x0403 0x6010
+# channel 1 does not have any functionality
+ftdi_channel 0
+# just TCK TDI TDO TMS, no reset
+ftdi_layout_init 0x0088 0x008b
+reset_config none
+
+# default speed
+adapter_khz 5000
diff --git a/openocd/xilinx-xc7.cfg b/openocd/xilinx-xc7.cfg
new file mode 100644
index 0000000..4c0502c
--- /dev/null
+++ b/openocd/xilinx-xc7.cfg
@@ -0,0 +1,65 @@
+# xilinx series 7 (artix, kintex, virtex)
+# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc7
+}
+
+# the 4 top bits (28:31) are the die stepping/revisions. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
+	-expected-id 0x03622093 \
+	-expected-id 0x03620093 \
+	-expected-id 0x037C4093 \
+	-expected-id 0x0362F093 \
+	-expected-id 0x037C8093 \
+	-expected-id 0x037C7093 \
+	-expected-id 0x037C3093 \
+	-expected-id 0x0362E093 \
+	-expected-id 0x037C2093 \
+	-expected-id 0x0362D093 \
+	-expected-id 0x0362C093 \
+	-expected-id 0x03632093 \
+	-expected-id 0x03631093 \
+	-expected-id 0x03636093 \
+	-expected-id 0x03647093 \
+	-expected-id 0x0364C093 \
+	-expected-id 0x03651093 \
+	-expected-id 0x03747093 \
+	-expected-id 0x03656093 \
+	-expected-id 0x03752093 \
+	-expected-id 0x03751093 \
+	-expected-id 0x03671093 \
+	-expected-id 0x036B3093 \
+	-expected-id 0x036B7093 \
+	-expected-id 0x036BB093 \
+	-expected-id 0x036BF093 \
+	-expected-id 0x03667093 \
+	-expected-id 0x03682093 \
+	-expected-id 0x03687093 \
+	-expected-id 0x03692093 \
+	-expected-id 0x03691093 \
+	-expected-id 0x03696093 \
+	-expected-id 0x036D5093 \
+	-expected-id 0x036D9093 \
+	-expected-id 0x036DB093
+
+pld device virtex2 $_CHIPNAME.tap 1
+
+set XC7_JSHUTDOWN 0x0d
+set XC7_JPROGRAM 0x0b
+set XC7_JSTART 0x0c
+set XC7_BYPASS 0x3f
+
+proc xc7_program {tap} {
+	global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
+	irscan $tap $XC7_JSHUTDOWN
+	irscan $tap $XC7_JPROGRAM
+	runtest 60000
+	#JSTART prevents this from working...
+	#irscan $tap $XC7_JSTART
+	runtest 2000
+	irscan $tap $XC7_BYPASS
+	runtest 2000
+}
diff --git a/pll/pll_bypass.v b/pll/pll_bypass.v
index 30bff07..11e85be 100644
--- a/pll/pll_bypass.v
+++ b/pll/pll_bypass.v
@@ -1,7 +1,7 @@
 module pll(
   input  clki,
-  output clko,
-  output lock
+  output reg clko,
+  output reg lock
 );
 
   always @* begin