mirror of
https://github.com/antonblanchard/chiselwatt.git
synced 2026-01-11 23:53:33 +00:00
Improve readme with Fusesoc info and update samples
Improved build instructions by using Fusesoc as package manager and multi-target toolchain. Updated hello_world sample app to fetch clock from SYSCON registers. Rebuilt all sample applications based on latest version and using SYSCON Improve Makefile build process for samples. Signed-off-by: Carlos de Paula <me@carlosedp.com>
This commit is contained in:
Carlos de Paula
parent
6d1d3e5670
commit
9eb5473a61
22
Makefile
22
Makefile
@ -119,20 +119,26 @@ apps_dir = ./samples
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hello_world:
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docker run -it --rm -w /build -v $(PWD):/build carlosedp/crossbuild-ppc64le make -C $(apps_dir)/hello_world
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@scripts/bin2hex.py $(apps_dir)/hello_world/hello_world.bin > ./insns.hex
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@cp -R $(apps_dir)/hello_world/hello_world.elf $(apps_dir)/binaries/hello_world
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@cp -R $(apps_dir)/hello_world/hello_world.bin $(apps_dir)/binaries/hello_world
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@scripts/bin2hex.py $(apps_dir)/binaries/hello_world/hello_world.bin > $(apps_dir)/binaries/hello_world/hello_world.hex
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@ln -sf $(apps_dir)/binaries/hello_world/hello_world.hex ./insns.hex
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micropython:
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@if [ ! -d "$(apps_dir)/micropyton/ports/powerpc" ] ; then \
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rm -rf $(apps_dir)/micropyton; \
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echo "Cloning micropython repo into $(apps_dir)/micropyton"; \
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git clone https://github.com/micropython/micropython.git $(apps_dir)/micropyton; \
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@if [ ! -d "$(apps_dir)/micropython/ports/powerpc" ] ; then \
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rm -rf $(apps_dir)/micropython; \
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echo "Cloning micropython repo into $(apps_dir)/micropython"; \
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git clone https://github.com/micropython/micropython.git $(apps_dir)/micropython; \
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else \
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echo "Micropython repo exists, updating..."; \
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cd "$(apps_dir)/micropyton"; \
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pushd "$(apps_dir)/micropython"; \
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git pull; \
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popd; \
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fi
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@docker run -it --rm -v $(PWD):/build carlosedp/crossbuild-ppc64le make -C $(apps_dir)/micropyton/ports/powerpc
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@scripts/bin2hex.py $(apps_dir)/micropyton/ports/powerpc/build/firmware.bin > ./insns.hex
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@docker run -it --rm -v $(PWD):/build carlosedp/crossbuild-ppc64le make -C $(apps_dir)/micropython/ports/powerpc
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@cp $(apps_dir)/micropython/ports/powerpc/build/firmware.bin $(apps_dir)/binaries/micropython
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@cp $(apps_dir)/micropython/ports/powerpc/build/firmware.elf $(apps_dir)/binaries/micropython
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@scripts/bin2hex.py $(apps_dir)/binaries/micropython/firmware.bin > $(apps_dir)/binaries/micropython/firmware.hex
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clean:
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@rm -f Core.fir firrtl_black_box_resource_files.f Core.v Core.anno.json MemoryBlackBox.v
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63
README.md
63
README.md
@ -41,29 +41,72 @@ make dockerlator
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exit
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```
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## Synthesizing for FPGAs using Open Source tools (yosys/nextpnr)
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## Synthesizing for FPGAs
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Synthesis on FPGAs is supported with yosys/nextpnr. At the moment the tools support
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Lattice ECP5 FPGAs. The build process uses Docker images, so no software other
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than Docker needs to be installed. If you prefer podman you can use that too,
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just adjust it in `Makefile`, `DOCKER=podman`.
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Synthesis on FPGAs is supported with [Fusesoc](https://github.com/olofk/fusesoc) to enable multiple targets and EDA backends. Fusesoc works with Edalize to provide package management and backend build for multiple FPGA vendors. At the moment the Chiselwatt supports some Xilinx, Lattice and Microchip FPGAs.
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### hello_world
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There is also a build process using Makefiles and Docker images, so no software other than Docker needs to be installed. If you prefer podman you can use that too, just adjust it in `Makefile`, `DOCKER=podman`.
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### Using Fusesoc
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Install Fusesoc with Python3 pip:
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```sh
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pip3 install fusesoc
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```
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Create a workspace and add Chiselwatt as a library:
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```sh
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mkdir workspace
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cd workspace
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fusesoc library add chiselwatt https://github.com/antonblanchard/chiselwatt
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fusesoc core list
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```
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Show all available targets:
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```sh
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fusesoc core show chiselwatt
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```
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Adjust memory requirements:
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The `hello_world` example should run everywhere, so start with it.
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Edit `src/main/scala/Core.scala` and set memory to 16 kB (`16*1024`):
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```scala
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(new ChiselStage).emitVerilog(new Core(64, 16*1024, "insns.hex", 0x0))
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(new ChiselStage).emitVerilog(new Core(64, 16*1024, "insns.hex", 0x0, 50000000))
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```
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Then link in the hello_world image:
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Build Chiselwatt (using mill, requires Java):
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```sh
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pushd fusesoc_libraries/chiselwatt
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# Link Hello World sample application
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ln -sf ./samples/binaries/hello_world/hello_world.hex ./insns.hex
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make
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popd
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# Build the project files for your target
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fusesoc run --target=polarfireeval_es chiselwatt
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```
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If you have the EDA tools installed, your core will be built, otherwise the project files will be placed in `build` directory.
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Some FPGA's, mainly Lattice using Yosys/NextPNR have a memory synthesys issue that restricts the use of Micropython.[see here](#Micropython).
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### Using the Makefile to build using Open Source tools (yosys/nextpnr)
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Link in the hello_world image:
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```sh
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ln -s samples/binaries/hello_world/hello_world.hex insns.hex
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```
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### Building and programming the FPGA
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#### Building and programming the FPGA
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The `Makefile` currently supports the following FPGA boards by defining the `ECP5_BOARD` parameter on make:
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@ -96,7 +139,7 @@ After programming, if you connect to the serial port of the FPGA at 115200 8n1,
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and after that all input will be echoed to the output. On Linux, picocom can be used.
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Another option below is a simple python script.
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### Micropython
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#### Micropython
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Unfortunately due to an issue in yosys/nextpnr, dual port RAMs are not
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working. More details can be found in <https://github.com/YosysHQ/yosys/issues/1101>.
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@ -1,8 +1,8 @@
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# build with docker build -t REPO/crossbuild-ppc64le -f Dockerfile.crossbuild-ppc64le .
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FROM debian:buster
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FROM python:3-buster
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ENV DEBIAN_FRONTEND noninteractive
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ENV TOOLCHAIN_URL https://toolchains.bootlin.com/downloads/releases/toolchains/powerpc64le-power8/tarballs/powerpc64le-power8--glibc--bleeding-edge-2020.02-2.tar.bz2
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ENV TOOLCHAIN_URL https://toolchains.bootlin.com/downloads/releases/toolchains/powerpc64le-power8/tarballs/powerpc64le-power8--glibc--bleeding-edge-2020.08-1.tar.bz2
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RUN apt-get update && \
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apt-get install -y --no-install-recommends \
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@ -24,7 +24,7 @@ RUN wget $TOOLCHAIN_URL && \
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tar vxf $(basename $TOOLCHAIN_URL) -C /opt/powerpc64le-toolchain --strip-components=1 && \
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rm -rf $(basename $TOOLCHAIN_URL)
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ENV PATH /opt/powerpc64le-toolchain/bin:$PATH
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ENV PATH $PATH:/opt/powerpc64le-toolchain/bin
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ENV CROSS_COMPILE powerpc64le-linux-
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RUN powerpc64le-linux-gcc --version
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@ -40,7 +40,7 @@ a64b5a7d14004a39
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60211f0064210000
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618c00003d800000
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658c0000798c07c6
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7d8903a6618c1194
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7d8903a6618c11ac
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480000004e800421
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0000000000000000
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0000000000000000
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@ -516,62 +516,65 @@ e8010010ebc1fff0
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3d20c0003842a000
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6129200060000000
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f922800079290020
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3940001a3d20c000
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7929002061292018
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4e800020f9490000
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0000000000000000
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3c40000100000000
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600000003842a000
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390a0010e9428000
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71290001e9280000
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e86a00084082fff8
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4e8000205463063e
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0000000000000000
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3c40000100000000
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600000003842a000
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390a0010e9428000
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71290008e9280000
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f86a00004082fff8
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3d40001c3d20c000
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e929000079290020
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3d40c0007d295392
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794a0020614a2018
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f92a00003929ffff
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000000004e800020
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0000000000000000
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3842a0003c400001
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fbc1fff07c0802a6
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7fc32214fbe1fff8
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f80100107c7f1b78
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7fbff040f821ffd1
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38210030409e000c
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887f00004bffff10
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4bffff993bff0001
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000000004bffffe4
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0000028001000000
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409e000c2f8a0000
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4e8000207d234b78
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4bffffe839290001
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e922800060000000
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e948000039090010
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4082fff8714a0001
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5463063ee8690008
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000000004e800020
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0000000000000000
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3842a0003c400001
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e922800060000000
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e948000039090010
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4082fff8714a0008
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4e800020f8690000
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0000000000000000
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3c40000100000000
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7c0802a63842a000
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fbe1fff8fbc1fff0
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7c7f1b787fc32214
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f821ffd1f8010010
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4082000c7c3ff040
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4bfffef438210030
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3bff0001887f0000
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4bffffe44bffff99
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0100000000000000
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7c691b7800000280
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7d4918ae38600000
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4d8200202c0a0000
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4bfffff038630001
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0000000000000000
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3c40000100000000
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7c0802a63842a000
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fbe1fff8fbc1fff0
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3be000007c7e1b78
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f821ffd1f8010010
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4bffffad7fc3f378
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4bfffe8c38210030
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4bffffb17fc3f378
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4181000c7c23f840
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4bfffe7438210030
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3bff00017c7ef8ae
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4bffffdc4bffff15
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4bffffdc4bffff19
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0100000000000000
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3c40000100000280
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7c0802a63842a000
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3fe2fffffbe1fff8
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f80100103bff7240
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4bfffe69f821ffd1
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386372003c62ffff
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f80100103bff7258
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4bfffe51f821ffd1
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386372183c62ffff
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3c62ffff4bffff85
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4bffff7938637238
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5463063e4bfffe8d
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409e00102b83000d
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4bffff7938637250
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5463063e4bfffe91
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408200102803000d
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4bffff617fe3fb78
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4bfffea94bffffe8
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4bfffead4bffffe8
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000000004bffffe0
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0000018001000000
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7266206f6c6c6548
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@ -586,21 +589,21 @@ f80100103bff7240
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0000000000000010
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0141780400527a01
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0000001000010c1b
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fffffdb000000018
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0000000000000040
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fffffd9800000018
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000000000000005c
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0000002c00000010
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00000038fffffddc
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00000038fffffde0
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0000001000000000
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fffffe0000000040
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fffffe0400000040
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0000000000000034
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0000005400000028
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00000050fffffe20
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00000050fffffe24
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9f029e0041094500
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437e4111300e4401
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4106dedf41000e0a
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000000100000000b
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fffffe4400000080
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000000000000002c
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fffffe4800000080
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0000000000000028
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0000009400000028
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00000058fffffe5c
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9f029e0041094500
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Binary file not shown.
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@ -9,7 +9,9 @@
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static uint64_t potato_uart_base;
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#define PROC_FREQ 50000000
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#define SYSCON_BASE 0xc0000000 /* System control regs */
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#define SYS_REG_CLKINFO 0x20
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#define UART_FREQ 115200
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#define UART_BASE 0xc0002000
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@ -93,9 +95,11 @@ static unsigned long potato_uart_divisor(unsigned long proc_freq, unsigned long
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void potato_uart_init(void)
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{
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uint64_t proc_freq;
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potato_uart_base = UART_BASE;
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potato_uart_reg_write(POTATO_CONSOLE_CLOCK_DIV, potato_uart_divisor(PROC_FREQ, UART_FREQ));
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proc_freq = *(volatile uint64_t *)(SYSCON_BASE + SYS_REG_CLKINFO);
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potato_uart_reg_write(POTATO_CONSOLE_CLOCK_DIV, potato_uart_divisor(proc_freq, UART_FREQ));
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}
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int getchar(void)
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@ -1 +0,0 @@
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Subproject commit 0bfd55afbe8eb798a806605a735fb3a68dee07a0
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@ -59,7 +59,7 @@ class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int, clockFr
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/* Blink an LED, this proves we are out of reset */
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val led = RegInit(0.U(1.W))
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val (counterValue, counterWrap) = Counter(true.B, 50000000)
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val (counterValue, counterWrap) = Counter(true.B, clockFreq)
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when (counterWrap) {
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led := ~led
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}
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