From 96fadc10d01a13b8c5235d29e69a4db72b914262 Mon Sep 17 00:00:00 2001 From: Carlos de Paula Date: Mon, 22 Feb 2021 11:03:31 -0300 Subject: [PATCH] Add post-build instructions for Polarfire Signed-off-by: Carlos de Paula --- chiselwatt.core | 11 ++++++++++- constraints/polarfire_eval.sdc | 1 + scripts/libero-post-instructions.txt | 13 +++++++++++++ 3 files changed, 24 insertions(+), 1 deletion(-) create mode 100644 constraints/polarfire_eval.sdc create mode 100644 scripts/libero-post-instructions.txt diff --git a/chiselwatt.core b/chiselwatt.core index 00ad7cb..d5b8f65 100644 --- a/chiselwatt.core +++ b/chiselwatt.core @@ -49,7 +49,10 @@ filesets: polarfireeval: files: - constraints/polarfire_eval.pdc: { file_type: PDC } + - constraints/polarfire_eval.sdc: { file_type: SDC } - pll/pll_polarfire50MHz.v: { file_type: verilogSource } + - scripts/libero-post-instructions.txt: + { file_type: user, copyto: post-instructions.txt } targets: cmod_a7-35: @@ -99,7 +102,9 @@ targets: polarfireeval: &polarfireeval default_tool: libero description: Microsemi Polarfire Evaluation Kit - filesets: [core, polarfireeval, micropython] + filesets: [core, polarfireeval, helloworld] + hooks: + post_run: [libero_post] tools: libero: &liberoMPF300 family: PolarFire @@ -119,3 +124,7 @@ parameters: datatype: bool description: External reset button polarity paramtype: generic + +scripts: + libero_post: + cmd: ["python3", "-c", "print(open('post-instructions.txt','r').read())"] diff --git a/constraints/polarfire_eval.sdc b/constraints/polarfire_eval.sdc new file mode 100644 index 0000000..53a4e89 --- /dev/null +++ b/constraints/polarfire_eval.sdc @@ -0,0 +1 @@ +create_clock -name {input} -period 20 -waveform {0 1.11111 } [ get_ports { clock } ] diff --git a/scripts/libero-post-instructions.txt b/scripts/libero-post-instructions.txt new file mode 100644 index 0000000..8b1a04d --- /dev/null +++ b/scripts/libero-post-instructions.txt @@ -0,0 +1,13 @@ +========================= +Libero build instructions +========================= + +After "Generate FPGA Array Data" task, open "Configure Design Initialization Data and Memories" tool. + +Click the "Fabric RAMs" tab and select "Initialize all clients from SPI-Flash" in the dropdown named "Initialize all clients from". + +Click "Apply". + +Select "Design Initialization" tab and set the dropdown "SPI Clock divider value" to "6 (13.33)". + +Click Apply