diff --git a/Makefile b/Makefile
index 2f191fd..2723cff 100644
--- a/Makefile
+++ b/Makefile
@@ -68,8 +68,8 @@ OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
 
 synth: chiselwatt.bit
 
-chiselwatt.json: $(verilog_files) insns.hex pll_ecp5_evn.v toplevel.v
-	$(YOSYS) -p "read_verilog -sv pll_ecp5_evn.v toplevel.v Core.v MemoryBlackBox.v; synth_ecp5 -json $@ -top toplevel"
+chiselwatt.json: $(verilog_files) insns.hex pll/pll_ehxplll.v toplevel.v
+	$(YOSYS) -p "read_verilog -sv pll/pll_ehxplll.v toplevel.v Core.v MemoryBlackBox.v; synth_ecp5 -json $@ -top toplevel"
 
 chiselwatt_out.config: chiselwatt.json $(LPF)
 	$(NEXTPNR) --json $< --lpf $(LPF) --textcfg $@ $(NEXTPNR_FLAGS) --package $(PACKAGE)
diff --git a/chiselwatt.core b/chiselwatt.core
index 85ff57c..edcafb3 100644
--- a/chiselwatt.core
+++ b/chiselwatt.core
@@ -14,12 +14,12 @@ filesets:
   cmod_a7-35:
     files:
       - constraints/cmod_a7-35.xdc : {file_type : xdc}
-      - pll_mmcme2.v : {file_type : verilogSource}
+      - pll/pll_mmcme2.v : {file_type : verilogSource}
 
   ecp5-evn:
     files:
       - constraints/ecp5-evn.lpf : {file_type : LPF}
-      - pll_ecp5_evn.v : {file_type : verilogSource}
+      - pll/pll_ehxplll.v : {file_type : verilogSource}
 
 targets:
   cmod_a7-35:
diff --git a/pll_ecp5_evn.v b/pll/pll_ehxplll.v
similarity index 100%
rename from pll_ecp5_evn.v
rename to pll/pll_ehxplll.v
diff --git a/pll_mmcme2.v b/pll/pll_mmcme2.v
similarity index 100%
rename from pll_mmcme2.v
rename to pll/pll_mmcme2.v