From d0a15b35de913ae19afb52ce150cecba0f6c4fcf Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Sun, 2 Feb 2020 09:42:15 +1100 Subject: [PATCH] Move PLLs into pll/ Also rename pll_ecp5_evn.v to pll_ehxplll.v Signed-off-by: Anton Blanchard --- Makefile | 4 ++-- chiselwatt.core | 4 ++-- pll_ecp5_evn.v => pll/pll_ehxplll.v | 0 pll_mmcme2.v => pll/pll_mmcme2.v | 0 4 files changed, 4 insertions(+), 4 deletions(-) rename pll_ecp5_evn.v => pll/pll_ehxplll.v (100%) rename pll_mmcme2.v => pll/pll_mmcme2.v (100%) diff --git a/Makefile b/Makefile index 2f191fd..2723cff 100644 --- a/Makefile +++ b/Makefile @@ -68,8 +68,8 @@ OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg synth: chiselwatt.bit -chiselwatt.json: $(verilog_files) insns.hex pll_ecp5_evn.v toplevel.v - $(YOSYS) -p "read_verilog -sv pll_ecp5_evn.v toplevel.v Core.v MemoryBlackBox.v; synth_ecp5 -json $@ -top toplevel" +chiselwatt.json: $(verilog_files) insns.hex pll/pll_ehxplll.v toplevel.v + $(YOSYS) -p "read_verilog -sv pll/pll_ehxplll.v toplevel.v Core.v MemoryBlackBox.v; synth_ecp5 -json $@ -top toplevel" chiselwatt_out.config: chiselwatt.json $(LPF) $(NEXTPNR) --json $< --lpf $(LPF) --textcfg $@ $(NEXTPNR_FLAGS) --package $(PACKAGE) diff --git a/chiselwatt.core b/chiselwatt.core index 85ff57c..edcafb3 100644 --- a/chiselwatt.core +++ b/chiselwatt.core @@ -14,12 +14,12 @@ filesets: cmod_a7-35: files: - constraints/cmod_a7-35.xdc : {file_type : xdc} - - pll_mmcme2.v : {file_type : verilogSource} + - pll/pll_mmcme2.v : {file_type : verilogSource} ecp5-evn: files: - constraints/ecp5-evn.lpf : {file_type : LPF} - - pll_ecp5_evn.v : {file_type : verilogSource} + - pll/pll_ehxplll.v : {file_type : verilogSource} targets: cmod_a7-35: diff --git a/pll_ecp5_evn.v b/pll/pll_ehxplll.v similarity index 100% rename from pll_ecp5_evn.v rename to pll/pll_ehxplll.v diff --git a/pll_mmcme2.v b/pll/pll_mmcme2.v similarity index 100% rename from pll_mmcme2.v rename to pll/pll_mmcme2.v