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committed by
Anton Blanchard
parent
43e1e73ce8
commit
d2e04d01ff
12
pll/pll_bypass.v
Normal file
12
pll/pll_bypass.v
Normal file
@@ -0,0 +1,12 @@
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module pll(
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input clki,
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output clko,
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output lock
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);
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always @* begin
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lock <= 1;
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clko <= clki;
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end
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endmodule
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