diff --git a/chiselwatt.core b/chiselwatt.core
new file mode 100644
index 0000000..85ff57c
--- /dev/null
+++ b/chiselwatt.core
@@ -0,0 +1,45 @@
+CAPI=2:
+
+name : ::chiselwatt:0
+
+filesets:
+  core:
+    files:
+      - Core.v
+      - MemoryBlackBox.v
+      - toplevel.v
+      - insns.hex : {copyto : insns.hex, file_type : user}
+    file_type : verilogSource
+
+  cmod_a7-35:
+    files:
+      - constraints/cmod_a7-35.xdc : {file_type : xdc}
+      - pll_mmcme2.v : {file_type : verilogSource}
+
+  ecp5-evn:
+    files:
+      - constraints/ecp5-evn.lpf : {file_type : LPF}
+      - pll_ecp5_evn.v : {file_type : verilogSource}
+
+targets:
+  cmod_a7-35:
+    default_tool: vivado
+    filesets: [core, cmod_a7-35]
+    parameters :
+      - RESET_LOW=false
+    tools:
+      vivado: {part : xc7a35tcpg236-1}
+    toplevel : toplevel
+
+  ecp5-evn:
+    default_tool: diamond
+    filesets: [core, ecp5-evn]
+    tools:
+      diamond: {part: LFE5U-85F-8BG381I}
+    toplevel : toplevel
+
+parameters:
+  RESET_LOW:
+    datatype    : bool
+    description : External reset button polarity
+    paramtype   : generic
diff --git a/constraints/cmod_a7-35.xdc b/constraints/cmod_a7-35.xdc
new file mode 100644
index 0000000..1048145
--- /dev/null
+++ b/constraints/cmod_a7-35.xdc
@@ -0,0 +1,20 @@
+## Clock signal 12 MHz
+set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports { clock }];
+create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {clock}];
+
+set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { io_tx }];
+set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { io_rx  }];
+
+set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports { reset }];
+
+set_property -dict { PACKAGE_PIN A17   IOSTANDARD LVCMOS33 } [get_ports { io_terminate }];
+
+set_property -dict { PACKAGE_PIN C16   IOSTANDARD LVCMOS33 } [get_ports { io_ledB }];
+set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVCMOS33 } [get_ports { io_ledC }];
+
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
+
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
+set_property CONFIG_MODE SPIx4 [current_design]
diff --git a/pll_mmcme2.v b/pll_mmcme2.v
new file mode 100644
index 0000000..ee4fc65
--- /dev/null
+++ b/pll_mmcme2.v
@@ -0,0 +1,22 @@
+module pll_ecp5_evn(input clki, output clko, output lock);
+
+wire clkfb;
+
+MMCME2_BASE #(
+        .BANDWIDTH("OPTIMIZED"),
+        .CLKFBOUT_MULT_F(50.0),
+        .CLKIN1_PERIOD(83.33),
+        .CLKOUT0_DIVIDE_F(12.0),
+        .DIVCLK_DIVIDE(1),
+        .STARTUP_WAIT("FALSE")
+    )
+    MMCME2_BASE_inst (
+        .CLKOUT0(clko),
+        .CLKFBOUT(clkfb),
+        .LOCKED(lock),
+        .CLKIN1(clki),
+        .PWRDWN(1'b0),
+        .RST(1'b0),
+        .CLKFBIN(clkfb)
+    );
+endmodule