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7f79b67019
This PR adds support for Polarfire FPGA from Microchip/Microsemi. The support has also been added to Fusesoc .core file to use the soon-to-be merged Libero backend. - Due to a tool incompatibility, Libero does not accept a module named "pll". Due to this, I've renamed the PLLs to Chiselwatt_pll. - Fixed formatting for chiselwatt.core file according to YAML lexer. - Added micropython and helloworls filesets to .core so it's possible to override the .hex to be used on core generation. Demo of hello_world and Micropython: https://twitter.com/carlosedp/status/1362119833324826626 Signed-off-by: Carlos de Paula <me@carlosedp.com>
10 lines
496 B
Plaintext
10 lines
496 B
Plaintext
set_io -port_name {clock} -pin_name E25 -io_std LVCMOS18 -fixed true
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set_io -port_name {reset} -pin_name K22 -io_std LVCMOS18 -fixed true
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set_io -port_name {io_tx} -pin_name G17 -io_std LVCMOS18 -fixed true
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set_io -port_name {io_rx} -pin_name H18 -io_std LVCMOS18 -fixed true
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set_io -port_name {io_terminate} -pin_name F22 -io_std LVCMOS18 -fixed true
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set_io -port_name {io_ledB} -pin_name B26 -io_std LVCMOS18 -fixed true
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set_io -port_name {io_ledC} -pin_name C26 -io_std LVCMOS18 -fixed true
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