mirror of
https://github.com/antonblanchard/chiselwatt.git
synced 2026-02-27 17:23:26 +00:00
14 lines
442 B
Plaintext
14 lines
442 B
Plaintext
=========================
|
|
Libero build instructions
|
|
=========================
|
|
|
|
After "Generate FPGA Array Data" task, open "Configure Design Initialization Data and Memories" tool.
|
|
|
|
Click the "Fabric RAMs" tab and select "Initialize all clients from SPI-Flash" in the dropdown named "Initialize all clients from".
|
|
|
|
Click "Apply".
|
|
|
|
Select "Design Initialization" tab and set the dropdown "SPI Clock divider value" to "6 (13.33)".
|
|
|
|
Click Apply
|