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27 lines
429 B
Verilog
27 lines
429 B
Verilog
module pll(
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input clki,
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output clko,
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output lock
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);
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wire clkfb;
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MMCME2_BASE #(
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.BANDWIDTH("OPTIMIZED"),
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.CLKFBOUT_MULT_F(50.0),
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.CLKIN1_PERIOD(83.33),
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.CLKOUT0_DIVIDE_F(12.0),
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.DIVCLK_DIVIDE(1),
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.STARTUP_WAIT("FALSE")
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) MMCME2_BASE_inst (
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.CLKOUT0(clko),
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.CLKFBOUT(clkfb),
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.LOCKED(lock),
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.CLKIN1(clki),
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.PWRDWN(1'b0),
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.RST(1'b0),
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.CLKFBIN(clkfb)
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);
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endmodule
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