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7f79b67019
This PR adds support for Polarfire FPGA from Microchip/Microsemi. The support has also been added to Fusesoc .core file to use the soon-to-be merged Libero backend. - Due to a tool incompatibility, Libero does not accept a module named "pll". Due to this, I've renamed the PLLs to Chiselwatt_pll. - Fixed formatting for chiselwatt.core file according to YAML lexer. - Added micropython and helloworls filesets to .core so it's possible to override the .hex to be used on core generation. Demo of hello_world and Micropython: https://twitter.com/carlosedp/status/1362119833324826626 Signed-off-by: Carlos de Paula <me@carlosedp.com>
13 lines
147 B
Verilog
13 lines
147 B
Verilog
module Chiselwatt_pll(
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input clki,
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output reg clko,
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output reg lock
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);
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always @* begin
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lock <= 1;
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clko <= clki;
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end
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endmodule
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