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https://github.com/antonblanchard/chiselwatt.git
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7f79b67019
This PR adds support for Polarfire FPGA from Microchip/Microsemi. The support has also been added to Fusesoc .core file to use the soon-to-be merged Libero backend. - Due to a tool incompatibility, Libero does not accept a module named "pll". Due to this, I've renamed the PLLs to Chiselwatt_pll. - Fixed formatting for chiselwatt.core file according to YAML lexer. - Added micropython and helloworls filesets to .core so it's possible to override the .hex to be used on core generation. Demo of hello_world and Micropython: https://twitter.com/carlosedp/status/1362119833324826626 Signed-off-by: Carlos de Paula <me@carlosedp.com>
37 lines
762 B
Verilog
37 lines
762 B
Verilog
module Chiselwatt_pll(
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input clki,
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output clko,
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output lock
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);
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(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
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EHXPLLL #(
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.PLLRST_ENA("DISABLED"),
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.INTFB_WAKE("DISABLED"),
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.STDBY_ENABLE("DISABLED"),
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.DPHASE_SOURCE("DISABLED"),
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.CLKOP_FPHASE(0),
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.CLKOP_CPHASE(11),
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.OUTDIVIDER_MUXA("DIVA"),
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.CLKOP_ENABLE("ENABLED"),
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.CLKOP_DIV(12),
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.CLKFB_DIV(25),
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.CLKI_DIV(6),
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.FEEDBK_PATH("CLKOP")
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) pll_i (
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.CLKI(clki),
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.CLKFB(clko),
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.CLKOP(clko),
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.LOCK(lock),
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.RST(1'b0),
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.STDBY(1'b0),
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.PHASESEL0(1'b0),
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.PHASESEL1(1'b0),
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.PHASEDIR(1'b0),
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.PHASESTEP(1'b0),
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.PLLWAKESYNC(1'b0),
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.ENCLKOP(1'b0)
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);
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endmodule
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