mirror of
https://github.com/antonblanchard/chiselwatt.git
synced 2026-01-13 15:27:47 +00:00
20 lines
956 B
Tcl
20 lines
956 B
Tcl
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clock }];
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create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { clock }];
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set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { reset }];
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set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { io_tx }];
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set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { io_rx }];
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set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { io_terminate }];
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set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { io_ledB }];
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set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { io_ledC }];
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property CFGBVS VCCO [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
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set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
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set_property CONFIG_MODE SPIx4 [current_design]
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