mirror of
https://github.com/antonblanchard/chiselwatt.git
synced 2026-01-13 15:27:47 +00:00
5fec805f65
This adds support for the rest of the divide instructions. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
111 lines
3.3 KiB
Scala
111 lines
3.3 KiB
Scala
import chisel3._
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import chisel3.util.{Valid, Decoupled, log2Ceil}
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class DividerInput(val bits: Int) extends Bundle {
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val dividend = UInt(bits.W)
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val divisor = UInt(bits.W)
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val is32bit = Bool()
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val signed = Bool()
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val extended = Bool()
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val modulus = Bool()
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}
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class SimpleDivider(val bits: Int) extends Module {
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val io = IO(new Bundle {
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val in = Flipped(Decoupled(new DividerInput(bits)))
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val out = Output(Valid(UInt(bits.W)))
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})
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val dividend = Reg(UInt((bits*2+1).W))
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val divisor = Reg(UInt(bits.W))
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val quotient = Reg(UInt(bits.W))
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val is32bit = Reg(Bool())
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val negativeResult = Reg(Bool())
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val signed = Reg(Bool())
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val modulus = Reg(Bool())
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val overflow = Reg(UInt(1.W))
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val overflow32 = Reg(UInt(1.W))
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val count = Reg(UInt(log2Ceil(bits+1).W))
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val busy = RegInit(false.B)
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io.in.ready := !busy
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when (io.in.valid && !busy) {
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when (io.in.bits.is32bit) {
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val dividendTemp = WireDefault(io.in.bits.dividend(31, 0))
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when (io.in.bits.signed) {
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dividendTemp := io.in.bits.dividend(31, 0).asSInt.abs().asUInt
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divisor := io.in.bits.divisor(31, 0).asSInt.abs().asUInt
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negativeResult := (io.in.bits.dividend(31) =/= io.in.bits.divisor(31))
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} .otherwise {
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divisor := io.in.bits.divisor(31, 0)
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negativeResult := 0.U
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}
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dividend := Mux(io.in.bits.extended, dividendTemp ## 0.U(32.W), dividendTemp)
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} .otherwise {
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val dividendTemp = WireDefault(io.in.bits.dividend)
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when (io.in.bits.signed) {
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dividendTemp := io.in.bits.dividend.asSInt.abs().asUInt
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divisor := io.in.bits.divisor.asSInt.abs().asUInt
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negativeResult := (io.in.bits.dividend(bits-1) =/= io.in.bits.divisor(bits-1))
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} .otherwise {
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divisor := io.in.bits.divisor
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negativeResult := 0.U
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}
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dividend := Mux(io.in.bits.extended, dividendTemp ## 0.U(bits.W), dividendTemp)
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}
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is32bit := io.in.bits.is32bit
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quotient := 0.U
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signed := io.in.bits.signed
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modulus := io.in.bits.modulus
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overflow := 0.U
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overflow32 := 0.U
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count := 0.U
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busy := true.B
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}
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when (busy) {
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when ((dividend(bits*2) === 1.U) || (dividend(bits*2-1, bits) >= divisor)) {
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dividend := (dividend(bits*2-1, bits) - divisor) ## dividend(bits-1, 0) ## 0.U(1.W)
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quotient := quotient(bits-2, 0) ## 1.U(1.W)
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} .otherwise {
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dividend := dividend((bits*2-1), 0) ## 0.U(1.W)
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quotient := quotient(bits-2, 0) ## 0.U(1.W)
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}
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overflow := quotient(bits-1)
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overflow32 := overflow32 | quotient(32-1)
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count := count + 1.U
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}
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val sResult = Mux(negativeResult, -(0.U(1.W) ## quotient), 0.U(1.W) ## quotient)
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// Catch unsigned and signed overflow, from Paul
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val resultOverflow = WireDefault(false.B)
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when (is32bit) {
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resultOverflow := overflow32.asBool || (signed && (sResult(32) ^ sResult(32-1)))
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} .otherwise {
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resultOverflow := overflow.asBool || (signed && (sResult(bits) ^ sResult(bits-1)))
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}
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val result = WireDefault(sResult(bits-1, 0))
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when (resultOverflow) {
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result := 0.U
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} .elsewhen (is32bit && !modulus) {
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result := sResult(31, 0)
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}
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io.out.bits := RegNext(result)
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io.out.valid := RegNext((count === (bits+1).U) && busy)
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when (io.out.valid) {
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busy := false.B
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}
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}
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object SimpleDividerObj extends App {
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chisel3.Driver.execute(Array[String](), () => new SimpleDivider(64))
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}
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