mirror of
https://github.com/antonblanchard/chiselwatt.git
synced 2026-01-29 21:31:14 +00:00
5a7fcbc814
This adds support for the cheap Colorlight 5A-75B ECP5 based board. UART RX is on J19, labelled key+ on the silk screen on the back UART TX is on J1, pin 1. All the I/Os on this board go through bidirectional level shifters that appear to be hardwired as outputs. To get an input pin for UART RX, we use the button I/O which is also routed to connector J19. The downside is we can't use the button for reset. One potential issue is that UART TX is 5V but UART RX is 3.3V. To keep the FPGA happy any attached UART chip needs to output 3.3V, but it also needs to be 5V tolerant to handle the level shifted input. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
97 lines
2.8 KiB
Makefile
97 lines
2.8 KiB
Makefile
all: chiselwatt
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scala_files = $(wildcard src/main/scala/*scala)
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verilog_files = Core.v MemoryBlackBox.v
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verilator_binary = chiselwatt
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$(verilog_files): $(scala_files)
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sbt 'runMain CoreObj'
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$(verilator_binary): $(verilog_files) chiselwatt.cpp uart.c
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# Warnings disabled until we fix the Chisel issues
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#verilator -O3 -Wall --assert --cc Core.v --exe chiselwatt.cpp uart.c #--trace
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verilator -O3 --assert --cc Core.v --exe chiselwatt.cpp uart.c -o $@ #--trace
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make -C obj_dir -f VCore.mk
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@cp -f obj_dir/chiselwatt chiselwatt
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clean:
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@rm -f Core.fir firrtl_black_box_resource_files.f Core.v Core.anno.json MemoryBlackBox.v
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@rm -rf obj_dir test_run_dir target project
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@rm -f chiselwatt
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@rm -f *.bit *.json *.svf *.config
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@rm -f LoadStoreInsns.hex MemoryBlackBoxInsns.hex
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scala_tests: $(verilator_binary)
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sbt testOnly
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tests = $(sort $(patsubst tests/%.out,%,$(wildcard tests/*.out)))
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check: scala_tests $(tests)
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$(tests): $(verilator_binary)
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@./scripts/run_test.sh $@
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# Use local tools for synthesis
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#YOSYS = yosys
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#NEXTPNR = nextpnr-ecp5
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#ECPPACK = ecppack
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#OPENOCD = openocd
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# Use Docker images for synthesis
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DOCKER=docker
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#DOCKER=podman
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#
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PWD = $(shell pwd)
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DOCKERARGS = run --rm -v $(PWD):/src -w /src
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#
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YOSYS = $(DOCKER) $(DOCKERARGS) ghdl/synth:beta yosys
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NEXTPNR = $(DOCKER) $(DOCKERARGS) ghdl/synth:nextpnr-ecp5 nextpnr-ecp5
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ECPPACK = $(DOCKER) $(DOCKERARGS) ghdl/synth:trellis ecppack
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OPENOCD = $(DOCKER) $(DOCKERARGS) --device /dev/bus/usb ghdl/synth:prog openocd
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# OrangeCrab with ECP85
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#LPF=constraints/orange-crab.lpf
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#PLL=pll/pll_bypass.v
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#PACKAGE=CSFBGA285
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#NEXTPNR_FLAGS=--um5g-85k --freq 50
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#OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg
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#OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
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# ECP5-EVN
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LPF=constraints/ecp5-evn.lpf
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PLL=pll/pll_ehxplll.v
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PACKAGE=CABGA381
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NEXTPNR_FLAGS=--um5g-85k --freq 12
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OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg
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OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
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# Colorlight 5A-75B
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#LPF=constraints/colorlight_5A-75B.lpf
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#PLL=pll/pll_ehxplll_25MHz.v
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#PACKAGE=CABGA256
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#NEXTPNR_FLAGS=--25k --freq 25
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#OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg
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#OPENOCD_DEVICE_CONFIG=openocd/LFE5U-25F.cfg
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synth: chiselwatt.bit
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chiselwatt.json: insns.hex $(verilog_files) $(PLL) toplevel.v
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$(YOSYS) -p "read_verilog -sv $(verilog_files) $(PLL) toplevel.v; synth_ecp5 -json $@ -top toplevel"
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chiselwatt_out.config: chiselwatt.json $(LPF)
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$(NEXTPNR) --json $< --lpf $(LPF) --textcfg $@ $(NEXTPNR_FLAGS) --package $(PACKAGE)
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chiselwatt.bit: chiselwatt_out.config
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$(ECPPACK) --svf chiselwatt.svf $< $@
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chiselwatt.svf: chiselwatt.bit
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prog: chiselwatt.svf
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$(OPENOCD) -f $(OPENOCD_JTAG_CONFIG) -f $(OPENOCD_DEVICE_CONFIG) -c "transport select jtag; init; svf $<; exit"
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.PHONY: clean prog
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.PRECIOUS: chiselwatt.json chiselwatt_out.config chiselwatt.bit
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