mirror of
https://github.com/antonblanchard/chiselwatt.git
synced 2026-01-13 15:27:47 +00:00
80d8e3a2cb
Since we are in raw mode, LR doesn't get converted into CR/LF. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
116 lines
2.2 KiB
C++
116 lines
2.2 KiB
C++
#include <stdlib.h>
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#include "VCore.h"
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#include "verilated.h"
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#include "verilated_vcd_c.h"
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/*
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* Current simulation time
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* This is a 64-bit integer to reduce wrap over issues and
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* allow modulus. You can also use a double, if you wish.
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*/
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vluint64_t main_time = 0;
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/*
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* Called by $time in Verilog
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* converts to double, to match
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* what SystemC does
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*/
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double sc_time_stamp(void)
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{
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return main_time;
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}
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#if VM_TRACE
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VerilatedVcdC *tfp;
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#endif
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void tick(VCore *top)
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{
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top->clock = 1;
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top->eval();
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#if VM_TRACE
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if (tfp)
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tfp->dump((double) main_time);
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#endif
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main_time++;
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top->clock = 0;
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top->eval();
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#if VM_TRACE
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if (tfp)
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tfp->dump((double) main_time);
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#endif
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main_time++;
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}
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void uart_tx(unsigned char tx);
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unsigned char uart_rx(void);
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int main(int argc, char **argv)
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{
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Verilated::commandArgs(argc, argv);
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// init top verilog instance
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VCore* top = new VCore;
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#if VM_TRACE
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// init trace dump
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Verilated::traceEverOn(true);
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tfp = new VerilatedVcdC;
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top->trace(tfp, 99);
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tfp->open("Core.vcd");
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#endif
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// Reset
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top->reset = 1;
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for (unsigned long i = 0; i < 5; i++)
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tick(top);
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top->reset = 0;
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while(!Verilated::gotFinish()) {
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tick(top);
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//VL_PRINTF("NIA %" VL_PRI64 "x\r\n", top->Core__DOT__executeNia);
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uart_tx(top->io_tx);
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top->io_rx = uart_rx();
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if (top->io_terminate) {
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for (unsigned long j = 0; j < 32; j++)
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VL_PRINTF("GPR%d %016" VL_PRI64 "X\r\n", j, top->Core__DOT__regFile__DOT__regs[j]);
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VL_PRINTF("CR 00000000%01X%01X%01X%01X%01X%01X%01X%01X\r\n",
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top->Core__DOT__conditionRegister_0,
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top->Core__DOT__conditionRegister_1,
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top->Core__DOT__conditionRegister_2,
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top->Core__DOT__conditionRegister_3,
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top->Core__DOT__conditionRegister_4,
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top->Core__DOT__conditionRegister_5,
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top->Core__DOT__conditionRegister_6,
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top->Core__DOT__conditionRegister_7);
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VL_PRINTF("LR %016" VL_PRI64 "X\r\n",
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top->Core__DOT__linkRegister);
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VL_PRINTF("CTR %016" VL_PRI64 "X\r\n",
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top->Core__DOT__countRegister);
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/*
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* We run for one more tick to allow any debug
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* prints in this cycle to make it out.
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*/
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tick(top);
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#if VM_TRACE
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tfp->close();
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#endif
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exit(1);
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}
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}
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#if VM_TRACE
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tfp->close();
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delete tfp;
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#endif
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delete top;
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}
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