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48 lines
585 B
Verilog
48 lines
585 B
Verilog
module toplevel(
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input clock,
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input reset,
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output io_tx,
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input io_rx,
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output io_terminate,
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output io_ledB,
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output io_ledC
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);
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wire clk_out;
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wire reset_out;
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wire lock;
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pll_ecp5_evn pll(
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.clki(clock),
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.clko(clock_out),
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.lock(lock),
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);
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Core core(
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.clock(clock_out),
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.reset(reset_out),
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.io_tx(io_tx),
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.io_rx(io_rx),
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.io_terminate(io_terminate),
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.io_ledB(io_ledB),
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.io_ledC(io_ledC)
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);
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logic [21:0] cnt = ~0;
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always_ff@(posedge clock)
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begin
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if (~lock || ~reset)
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begin
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cnt <= ~0;
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end
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else if (cnt)
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begin
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cnt <= cnt - 1;
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end
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reset_out <= |cnt;
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end
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endmodule
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