//--------------------------------------------------------------------------------
// Auto-generated by Migen (0d16e03) & LiteX (3391398a) on 2020-05-21 19:21:29
//--------------------------------------------------------------------------------
module litedram_core(
	input wire clk,
	input wire rst,
	output wire pll_locked,
	output wire [14:0] ddram_a,
	output wire [2:0] ddram_ba,
	output wire ddram_ras_n,
	output wire ddram_cas_n,
	output wire ddram_we_n,
	output wire ddram_cs_n,
	output wire [1:0] ddram_dm,
	inout wire [15:0] ddram_dq,
	inout wire [1:0] ddram_dqs_p,
	inout wire [1:0] ddram_dqs_n,
	output wire ddram_clk_p,
	output wire ddram_clk_n,
	output wire ddram_cke,
	output wire ddram_odt,
	output wire ddram_reset_n,
	output wire init_done,
	output wire init_error,
	input wire [29:0] wb_ctrl_adr,
	input wire [31:0] wb_ctrl_dat_w,
	output wire [31:0] wb_ctrl_dat_r,
	input wire [3:0] wb_ctrl_sel,
	input wire wb_ctrl_cyc,
	input wire wb_ctrl_stb,
	output wire wb_ctrl_ack,
	input wire wb_ctrl_we,
	input wire [2:0] wb_ctrl_cti,
	input wire [1:0] wb_ctrl_bte,
	output wire wb_ctrl_err,
	output wire user_clk,
	output wire user_rst,
	input wire user_port_native_0_cmd_valid,
	output wire user_port_native_0_cmd_ready,
	input wire user_port_native_0_cmd_we,
	input wire [24:0] user_port_native_0_cmd_addr,
	input wire user_port_native_0_wdata_valid,
	output wire user_port_native_0_wdata_ready,
	input wire [15:0] user_port_native_0_wdata_we,
	input wire [127:0] user_port_native_0_wdata_data,
	output wire user_port_native_0_rdata_valid,
	input wire user_port_native_0_rdata_ready,
	output wire [127:0] user_port_native_0_rdata_data
);

reg [13:0] litedramcore_adr = 14'd0;
reg litedramcore_we = 1'd0;
wire [31:0] litedramcore_dat_w;
wire [31:0] litedramcore_dat_r;
wire [29:0] litedramcore_wishbone_adr;
wire [31:0] litedramcore_wishbone_dat_w;
wire [31:0] litedramcore_wishbone_dat_r;
wire [3:0] litedramcore_wishbone_sel;
wire litedramcore_wishbone_cyc;
wire litedramcore_wishbone_stb;
reg litedramcore_wishbone_ack = 1'd0;
wire litedramcore_wishbone_we;
wire [2:0] litedramcore_wishbone_cti;
wire [1:0] litedramcore_wishbone_bte;
reg litedramcore_wishbone_err = 1'd0;
wire sys_clk;
wire sys_rst;
wire sys4x_clk;
wire sys4x_dqs_clk;
wire iodelay_clk;
wire iodelay_rst;
wire sys_pll_reset;
wire sys_pll_locked;
wire s7pll0_clkin;
wire s7pll0_clkout0;
wire s7pll0_clkout_buf0;
wire s7pll0_clkout1;
wire s7pll0_clkout_buf1;
wire s7pll0_clkout2;
wire s7pll0_clkout_buf2;
wire iodelay_pll_reset;
wire iodelay_pll_locked;
wire s7pll1_clkin;
wire s7pll1_clkout;
wire s7pll1_clkout_buf;
reg [3:0] reset_counter = 4'd15;
reg ic_reset = 1'd1;
reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8;
reg a7ddrphy_half_sys8x_taps_re = 1'd0;
reg a7ddrphy_wlevel_en_storage = 1'd0;
reg a7ddrphy_wlevel_en_re = 1'd0;
wire a7ddrphy_wlevel_strobe_re;
wire a7ddrphy_wlevel_strobe_r;
wire a7ddrphy_wlevel_strobe_we;
reg a7ddrphy_wlevel_strobe_w = 1'd0;
wire a7ddrphy_cdly_rst_re;
wire a7ddrphy_cdly_rst_r;
wire a7ddrphy_cdly_rst_we;
reg a7ddrphy_cdly_rst_w = 1'd0;
wire a7ddrphy_cdly_inc_re;
wire a7ddrphy_cdly_inc_r;
wire a7ddrphy_cdly_inc_we;
reg a7ddrphy_cdly_inc_w = 1'd0;
reg [1:0] a7ddrphy_dly_sel_storage = 2'd0;
reg a7ddrphy_dly_sel_re = 1'd0;
wire a7ddrphy_rdly_dq_rst_re;
wire a7ddrphy_rdly_dq_rst_r;
wire a7ddrphy_rdly_dq_rst_we;
reg a7ddrphy_rdly_dq_rst_w = 1'd0;
wire a7ddrphy_rdly_dq_inc_re;
wire a7ddrphy_rdly_dq_inc_r;
wire a7ddrphy_rdly_dq_inc_we;
reg a7ddrphy_rdly_dq_inc_w = 1'd0;
wire a7ddrphy_rdly_dq_bitslip_rst_re;
wire a7ddrphy_rdly_dq_bitslip_rst_r;
wire a7ddrphy_rdly_dq_bitslip_rst_we;
reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
wire a7ddrphy_rdly_dq_bitslip_re;
wire a7ddrphy_rdly_dq_bitslip_r;
wire a7ddrphy_rdly_dq_bitslip_we;
reg a7ddrphy_rdly_dq_bitslip_w = 1'd0;
wire [14:0] a7ddrphy_dfi_p0_address;
wire [2:0] a7ddrphy_dfi_p0_bank;
wire a7ddrphy_dfi_p0_cas_n;
wire a7ddrphy_dfi_p0_cs_n;
wire a7ddrphy_dfi_p0_ras_n;
wire a7ddrphy_dfi_p0_we_n;
wire a7ddrphy_dfi_p0_cke;
wire a7ddrphy_dfi_p0_odt;
wire a7ddrphy_dfi_p0_reset_n;
wire a7ddrphy_dfi_p0_act_n;
wire [31:0] a7ddrphy_dfi_p0_wrdata;
wire a7ddrphy_dfi_p0_wrdata_en;
wire [3:0] a7ddrphy_dfi_p0_wrdata_mask;
wire a7ddrphy_dfi_p0_rddata_en;
reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0;
reg a7ddrphy_dfi_p0_rddata_valid = 1'd0;
wire [14:0] a7ddrphy_dfi_p1_address;
wire [2:0] a7ddrphy_dfi_p1_bank;
wire a7ddrphy_dfi_p1_cas_n;
wire a7ddrphy_dfi_p1_cs_n;
wire a7ddrphy_dfi_p1_ras_n;
wire a7ddrphy_dfi_p1_we_n;
wire a7ddrphy_dfi_p1_cke;
wire a7ddrphy_dfi_p1_odt;
wire a7ddrphy_dfi_p1_reset_n;
wire a7ddrphy_dfi_p1_act_n;
wire [31:0] a7ddrphy_dfi_p1_wrdata;
wire a7ddrphy_dfi_p1_wrdata_en;
wire [3:0] a7ddrphy_dfi_p1_wrdata_mask;
wire a7ddrphy_dfi_p1_rddata_en;
reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0;
reg a7ddrphy_dfi_p1_rddata_valid = 1'd0;
wire [14:0] a7ddrphy_dfi_p2_address;
wire [2:0] a7ddrphy_dfi_p2_bank;
wire a7ddrphy_dfi_p2_cas_n;
wire a7ddrphy_dfi_p2_cs_n;
wire a7ddrphy_dfi_p2_ras_n;
wire a7ddrphy_dfi_p2_we_n;
wire a7ddrphy_dfi_p2_cke;
wire a7ddrphy_dfi_p2_odt;
wire a7ddrphy_dfi_p2_reset_n;
wire a7ddrphy_dfi_p2_act_n;
wire [31:0] a7ddrphy_dfi_p2_wrdata;
wire a7ddrphy_dfi_p2_wrdata_en;
wire [3:0] a7ddrphy_dfi_p2_wrdata_mask;
wire a7ddrphy_dfi_p2_rddata_en;
reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0;
reg a7ddrphy_dfi_p2_rddata_valid = 1'd0;
wire [14:0] a7ddrphy_dfi_p3_address;
wire [2:0] a7ddrphy_dfi_p3_bank;
wire a7ddrphy_dfi_p3_cas_n;
wire a7ddrphy_dfi_p3_cs_n;
wire a7ddrphy_dfi_p3_ras_n;
wire a7ddrphy_dfi_p3_we_n;
wire a7ddrphy_dfi_p3_cke;
wire a7ddrphy_dfi_p3_odt;
wire a7ddrphy_dfi_p3_reset_n;
wire a7ddrphy_dfi_p3_act_n;
wire [31:0] a7ddrphy_dfi_p3_wrdata;
wire a7ddrphy_dfi_p3_wrdata_en;
wire [3:0] a7ddrphy_dfi_p3_wrdata_mask;
wire a7ddrphy_dfi_p3_rddata_en;
reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0;
reg a7ddrphy_dfi_p3_rddata_valid = 1'd0;
wire a7ddrphy_sd_clk_se_nodelay;
reg a7ddrphy_dqs_oe = 1'd0;
reg a7ddrphy_dqs_oe_delayed = 1'd0;
wire a7ddrphy_dqspattern0;
wire a7ddrphy_dqspattern1;
reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0;
reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0;
wire [1:0] a7ddrphy_dqs_i;
wire [1:0] a7ddrphy_dqs_i_delayed;
wire a7ddrphy_dqs_o_no_delay0;
wire a7ddrphy_dqs_t0;
wire a7ddrphy0;
wire a7ddrphy_dqs_o_no_delay1;
wire a7ddrphy_dqs_t1;
wire a7ddrphy1;
wire a7ddrphy_dq_oe;
reg a7ddrphy_dq_oe_delayed = 1'd0;
wire a7ddrphy_dq_o_nodelay0;
wire a7ddrphy_dq_i_nodelay0;
wire a7ddrphy_dq_i_delayed0;
wire a7ddrphy_dq_t0;
wire [7:0] a7ddrphy_dq_i_data0;
wire [7:0] a7ddrphy_bitslip0_i;
reg [7:0] a7ddrphy_bitslip0_o = 8'd0;
reg [3:0] a7ddrphy_bitslip0_value = 4'd0;
reg [23:0] a7ddrphy_bitslip0_r = 24'd0;
wire a7ddrphy_dq_o_nodelay1;
wire a7ddrphy_dq_i_nodelay1;
wire a7ddrphy_dq_i_delayed1;
wire a7ddrphy_dq_t1;
wire [7:0] a7ddrphy_dq_i_data1;
wire [7:0] a7ddrphy_bitslip1_i;
reg [7:0] a7ddrphy_bitslip1_o = 8'd0;
reg [3:0] a7ddrphy_bitslip1_value = 4'd0;
reg [23:0] a7ddrphy_bitslip1_r = 24'd0;
wire a7ddrphy_dq_o_nodelay2;
wire a7ddrphy_dq_i_nodelay2;
wire a7ddrphy_dq_i_delayed2;
wire a7ddrphy_dq_t2;
wire [7:0] a7ddrphy_dq_i_data2;
wire [7:0] a7ddrphy_bitslip2_i;
reg [7:0] a7ddrphy_bitslip2_o = 8'd0;
reg [3:0] a7ddrphy_bitslip2_value = 4'd0;
reg [23:0] a7ddrphy_bitslip2_r = 24'd0;
wire a7ddrphy_dq_o_nodelay3;
wire a7ddrphy_dq_i_nodelay3;
wire a7ddrphy_dq_i_delayed3;
wire a7ddrphy_dq_t3;
wire [7:0] a7ddrphy_dq_i_data3;
wire [7:0] a7ddrphy_bitslip3_i;
reg [7:0] a7ddrphy_bitslip3_o = 8'd0;
reg [3:0] a7ddrphy_bitslip3_value = 4'd0;
reg [23:0] a7ddrphy_bitslip3_r = 24'd0;
wire a7ddrphy_dq_o_nodelay4;
wire a7ddrphy_dq_i_nodelay4;
wire a7ddrphy_dq_i_delayed4;
wire a7ddrphy_dq_t4;
wire [7:0] a7ddrphy_dq_i_data4;
wire [7:0] a7ddrphy_bitslip4_i;
reg [7:0] a7ddrphy_bitslip4_o = 8'd0;
reg [3:0] a7ddrphy_bitslip4_value = 4'd0;
reg [23:0] a7ddrphy_bitslip4_r = 24'd0;
wire a7ddrphy_dq_o_nodelay5;
wire a7ddrphy_dq_i_nodelay5;
wire a7ddrphy_dq_i_delayed5;
wire a7ddrphy_dq_t5;
wire [7:0] a7ddrphy_dq_i_data5;
wire [7:0] a7ddrphy_bitslip5_i;
reg [7:0] a7ddrphy_bitslip5_o = 8'd0;
reg [3:0] a7ddrphy_bitslip5_value = 4'd0;
reg [23:0] a7ddrphy_bitslip5_r = 24'd0;
wire a7ddrphy_dq_o_nodelay6;
wire a7ddrphy_dq_i_nodelay6;
wire a7ddrphy_dq_i_delayed6;
wire a7ddrphy_dq_t6;
wire [7:0] a7ddrphy_dq_i_data6;
wire [7:0] a7ddrphy_bitslip6_i;
reg [7:0] a7ddrphy_bitslip6_o = 8'd0;
reg [3:0] a7ddrphy_bitslip6_value = 4'd0;
reg [23:0] a7ddrphy_bitslip6_r = 24'd0;
wire a7ddrphy_dq_o_nodelay7;
wire a7ddrphy_dq_i_nodelay7;
wire a7ddrphy_dq_i_delayed7;
wire a7ddrphy_dq_t7;
wire [7:0] a7ddrphy_dq_i_data7;
wire [7:0] a7ddrphy_bitslip7_i;
reg [7:0] a7ddrphy_bitslip7_o = 8'd0;
reg [3:0] a7ddrphy_bitslip7_value = 4'd0;
reg [23:0] a7ddrphy_bitslip7_r = 24'd0;
wire a7ddrphy_dq_o_nodelay8;
wire a7ddrphy_dq_i_nodelay8;
wire a7ddrphy_dq_i_delayed8;
wire a7ddrphy_dq_t8;
wire [7:0] a7ddrphy_dq_i_data8;
wire [7:0] a7ddrphy_bitslip8_i;
reg [7:0] a7ddrphy_bitslip8_o = 8'd0;
reg [3:0] a7ddrphy_bitslip8_value = 4'd0;
reg [23:0] a7ddrphy_bitslip8_r = 24'd0;
wire a7ddrphy_dq_o_nodelay9;
wire a7ddrphy_dq_i_nodelay9;
wire a7ddrphy_dq_i_delayed9;
wire a7ddrphy_dq_t9;
wire [7:0] a7ddrphy_dq_i_data9;
wire [7:0] a7ddrphy_bitslip9_i;
reg [7:0] a7ddrphy_bitslip9_o = 8'd0;
reg [3:0] a7ddrphy_bitslip9_value = 4'd0;
reg [23:0] a7ddrphy_bitslip9_r = 24'd0;
wire a7ddrphy_dq_o_nodelay10;
wire a7ddrphy_dq_i_nodelay10;
wire a7ddrphy_dq_i_delayed10;
wire a7ddrphy_dq_t10;
wire [7:0] a7ddrphy_dq_i_data10;
wire [7:0] a7ddrphy_bitslip10_i;
reg [7:0] a7ddrphy_bitslip10_o = 8'd0;
reg [3:0] a7ddrphy_bitslip10_value = 4'd0;
reg [23:0] a7ddrphy_bitslip10_r = 24'd0;
wire a7ddrphy_dq_o_nodelay11;
wire a7ddrphy_dq_i_nodelay11;
wire a7ddrphy_dq_i_delayed11;
wire a7ddrphy_dq_t11;
wire [7:0] a7ddrphy_dq_i_data11;
wire [7:0] a7ddrphy_bitslip11_i;
reg [7:0] a7ddrphy_bitslip11_o = 8'd0;
reg [3:0] a7ddrphy_bitslip11_value = 4'd0;
reg [23:0] a7ddrphy_bitslip11_r = 24'd0;
wire a7ddrphy_dq_o_nodelay12;
wire a7ddrphy_dq_i_nodelay12;
wire a7ddrphy_dq_i_delayed12;
wire a7ddrphy_dq_t12;
wire [7:0] a7ddrphy_dq_i_data12;
wire [7:0] a7ddrphy_bitslip12_i;
reg [7:0] a7ddrphy_bitslip12_o = 8'd0;
reg [3:0] a7ddrphy_bitslip12_value = 4'd0;
reg [23:0] a7ddrphy_bitslip12_r = 24'd0;
wire a7ddrphy_dq_o_nodelay13;
wire a7ddrphy_dq_i_nodelay13;
wire a7ddrphy_dq_i_delayed13;
wire a7ddrphy_dq_t13;
wire [7:0] a7ddrphy_dq_i_data13;
wire [7:0] a7ddrphy_bitslip13_i;
reg [7:0] a7ddrphy_bitslip13_o = 8'd0;
reg [3:0] a7ddrphy_bitslip13_value = 4'd0;
reg [23:0] a7ddrphy_bitslip13_r = 24'd0;
wire a7ddrphy_dq_o_nodelay14;
wire a7ddrphy_dq_i_nodelay14;
wire a7ddrphy_dq_i_delayed14;
wire a7ddrphy_dq_t14;
wire [7:0] a7ddrphy_dq_i_data14;
wire [7:0] a7ddrphy_bitslip14_i;
reg [7:0] a7ddrphy_bitslip14_o = 8'd0;
reg [3:0] a7ddrphy_bitslip14_value = 4'd0;
reg [23:0] a7ddrphy_bitslip14_r = 24'd0;
wire a7ddrphy_dq_o_nodelay15;
wire a7ddrphy_dq_i_nodelay15;
wire a7ddrphy_dq_i_delayed15;
wire a7ddrphy_dq_t15;
wire [7:0] a7ddrphy_dq_i_data15;
wire [7:0] a7ddrphy_bitslip15_i;
reg [7:0] a7ddrphy_bitslip15_o = 8'd0;
reg [3:0] a7ddrphy_bitslip15_value = 4'd0;
reg [23:0] a7ddrphy_bitslip15_r = 24'd0;
wire [7:0] a7ddrphy_rddata_en;
reg [7:0] a7ddrphy_rddata_en_last = 8'd0;
wire [3:0] a7ddrphy_wrdata_en;
reg [3:0] a7ddrphy_wrdata_en_last = 4'd0;
wire [14:0] litedramcore_inti_p0_address;
wire [2:0] litedramcore_inti_p0_bank;
reg litedramcore_inti_p0_cas_n = 1'd1;
reg litedramcore_inti_p0_cs_n = 1'd1;
reg litedramcore_inti_p0_ras_n = 1'd1;
reg litedramcore_inti_p0_we_n = 1'd1;
wire litedramcore_inti_p0_cke;
wire litedramcore_inti_p0_odt;
wire litedramcore_inti_p0_reset_n;
reg litedramcore_inti_p0_act_n = 1'd1;
wire [31:0] litedramcore_inti_p0_wrdata;
wire litedramcore_inti_p0_wrdata_en;
wire [3:0] litedramcore_inti_p0_wrdata_mask;
wire litedramcore_inti_p0_rddata_en;
reg [31:0] litedramcore_inti_p0_rddata = 32'd0;
reg litedramcore_inti_p0_rddata_valid = 1'd0;
wire [14:0] litedramcore_inti_p1_address;
wire [2:0] litedramcore_inti_p1_bank;
reg litedramcore_inti_p1_cas_n = 1'd1;
reg litedramcore_inti_p1_cs_n = 1'd1;
reg litedramcore_inti_p1_ras_n = 1'd1;
reg litedramcore_inti_p1_we_n = 1'd1;
wire litedramcore_inti_p1_cke;
wire litedramcore_inti_p1_odt;
wire litedramcore_inti_p1_reset_n;
reg litedramcore_inti_p1_act_n = 1'd1;
wire [31:0] litedramcore_inti_p1_wrdata;
wire litedramcore_inti_p1_wrdata_en;
wire [3:0] litedramcore_inti_p1_wrdata_mask;
wire litedramcore_inti_p1_rddata_en;
reg [31:0] litedramcore_inti_p1_rddata = 32'd0;
reg litedramcore_inti_p1_rddata_valid = 1'd0;
wire [14:0] litedramcore_inti_p2_address;
wire [2:0] litedramcore_inti_p2_bank;
reg litedramcore_inti_p2_cas_n = 1'd1;
reg litedramcore_inti_p2_cs_n = 1'd1;
reg litedramcore_inti_p2_ras_n = 1'd1;
reg litedramcore_inti_p2_we_n = 1'd1;
wire litedramcore_inti_p2_cke;
wire litedramcore_inti_p2_odt;
wire litedramcore_inti_p2_reset_n;
reg litedramcore_inti_p2_act_n = 1'd1;
wire [31:0] litedramcore_inti_p2_wrdata;
wire litedramcore_inti_p2_wrdata_en;
wire [3:0] litedramcore_inti_p2_wrdata_mask;
wire litedramcore_inti_p2_rddata_en;
reg [31:0] litedramcore_inti_p2_rddata = 32'd0;
reg litedramcore_inti_p2_rddata_valid = 1'd0;
wire [14:0] litedramcore_inti_p3_address;
wire [2:0] litedramcore_inti_p3_bank;
reg litedramcore_inti_p3_cas_n = 1'd1;
reg litedramcore_inti_p3_cs_n = 1'd1;
reg litedramcore_inti_p3_ras_n = 1'd1;
reg litedramcore_inti_p3_we_n = 1'd1;
wire litedramcore_inti_p3_cke;
wire litedramcore_inti_p3_odt;
wire litedramcore_inti_p3_reset_n;
reg litedramcore_inti_p3_act_n = 1'd1;
wire [31:0] litedramcore_inti_p3_wrdata;
wire litedramcore_inti_p3_wrdata_en;
wire [3:0] litedramcore_inti_p3_wrdata_mask;
wire litedramcore_inti_p3_rddata_en;
reg [31:0] litedramcore_inti_p3_rddata = 32'd0;
reg litedramcore_inti_p3_rddata_valid = 1'd0;
wire [14:0] litedramcore_slave_p0_address;
wire [2:0] litedramcore_slave_p0_bank;
wire litedramcore_slave_p0_cas_n;
wire litedramcore_slave_p0_cs_n;
wire litedramcore_slave_p0_ras_n;
wire litedramcore_slave_p0_we_n;
wire litedramcore_slave_p0_cke;
wire litedramcore_slave_p0_odt;
wire litedramcore_slave_p0_reset_n;
wire litedramcore_slave_p0_act_n;
wire [31:0] litedramcore_slave_p0_wrdata;
wire litedramcore_slave_p0_wrdata_en;
wire [3:0] litedramcore_slave_p0_wrdata_mask;
wire litedramcore_slave_p0_rddata_en;
reg [31:0] litedramcore_slave_p0_rddata = 32'd0;
reg litedramcore_slave_p0_rddata_valid = 1'd0;
wire [14:0] litedramcore_slave_p1_address;
wire [2:0] litedramcore_slave_p1_bank;
wire litedramcore_slave_p1_cas_n;
wire litedramcore_slave_p1_cs_n;
wire litedramcore_slave_p1_ras_n;
wire litedramcore_slave_p1_we_n;
wire litedramcore_slave_p1_cke;
wire litedramcore_slave_p1_odt;
wire litedramcore_slave_p1_reset_n;
wire litedramcore_slave_p1_act_n;
wire [31:0] litedramcore_slave_p1_wrdata;
wire litedramcore_slave_p1_wrdata_en;
wire [3:0] litedramcore_slave_p1_wrdata_mask;
wire litedramcore_slave_p1_rddata_en;
reg [31:0] litedramcore_slave_p1_rddata = 32'd0;
reg litedramcore_slave_p1_rddata_valid = 1'd0;
wire [14:0] litedramcore_slave_p2_address;
wire [2:0] litedramcore_slave_p2_bank;
wire litedramcore_slave_p2_cas_n;
wire litedramcore_slave_p2_cs_n;
wire litedramcore_slave_p2_ras_n;
wire litedramcore_slave_p2_we_n;
wire litedramcore_slave_p2_cke;
wire litedramcore_slave_p2_odt;
wire litedramcore_slave_p2_reset_n;
wire litedramcore_slave_p2_act_n;
wire [31:0] litedramcore_slave_p2_wrdata;
wire litedramcore_slave_p2_wrdata_en;
wire [3:0] litedramcore_slave_p2_wrdata_mask;
wire litedramcore_slave_p2_rddata_en;
reg [31:0] litedramcore_slave_p2_rddata = 32'd0;
reg litedramcore_slave_p2_rddata_valid = 1'd0;
wire [14:0] litedramcore_slave_p3_address;
wire [2:0] litedramcore_slave_p3_bank;
wire litedramcore_slave_p3_cas_n;
wire litedramcore_slave_p3_cs_n;
wire litedramcore_slave_p3_ras_n;
wire litedramcore_slave_p3_we_n;
wire litedramcore_slave_p3_cke;
wire litedramcore_slave_p3_odt;
wire litedramcore_slave_p3_reset_n;
wire litedramcore_slave_p3_act_n;
wire [31:0] litedramcore_slave_p3_wrdata;
wire litedramcore_slave_p3_wrdata_en;
wire [3:0] litedramcore_slave_p3_wrdata_mask;
wire litedramcore_slave_p3_rddata_en;
reg [31:0] litedramcore_slave_p3_rddata = 32'd0;
reg litedramcore_slave_p3_rddata_valid = 1'd0;
reg [14:0] litedramcore_master_p0_address = 15'd0;
reg [2:0] litedramcore_master_p0_bank = 3'd0;
reg litedramcore_master_p0_cas_n = 1'd1;
reg litedramcore_master_p0_cs_n = 1'd1;
reg litedramcore_master_p0_ras_n = 1'd1;
reg litedramcore_master_p0_we_n = 1'd1;
reg litedramcore_master_p0_cke = 1'd0;
reg litedramcore_master_p0_odt = 1'd0;
reg litedramcore_master_p0_reset_n = 1'd0;
reg litedramcore_master_p0_act_n = 1'd1;
reg [31:0] litedramcore_master_p0_wrdata = 32'd0;
reg litedramcore_master_p0_wrdata_en = 1'd0;
reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0;
reg litedramcore_master_p0_rddata_en = 1'd0;
wire [31:0] litedramcore_master_p0_rddata;
wire litedramcore_master_p0_rddata_valid;
reg [14:0] litedramcore_master_p1_address = 15'd0;
reg [2:0] litedramcore_master_p1_bank = 3'd0;
reg litedramcore_master_p1_cas_n = 1'd1;
reg litedramcore_master_p1_cs_n = 1'd1;
reg litedramcore_master_p1_ras_n = 1'd1;
reg litedramcore_master_p1_we_n = 1'd1;
reg litedramcore_master_p1_cke = 1'd0;
reg litedramcore_master_p1_odt = 1'd0;
reg litedramcore_master_p1_reset_n = 1'd0;
reg litedramcore_master_p1_act_n = 1'd1;
reg [31:0] litedramcore_master_p1_wrdata = 32'd0;
reg litedramcore_master_p1_wrdata_en = 1'd0;
reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0;
reg litedramcore_master_p1_rddata_en = 1'd0;
wire [31:0] litedramcore_master_p1_rddata;
wire litedramcore_master_p1_rddata_valid;
reg [14:0] litedramcore_master_p2_address = 15'd0;
reg [2:0] litedramcore_master_p2_bank = 3'd0;
reg litedramcore_master_p2_cas_n = 1'd1;
reg litedramcore_master_p2_cs_n = 1'd1;
reg litedramcore_master_p2_ras_n = 1'd1;
reg litedramcore_master_p2_we_n = 1'd1;
reg litedramcore_master_p2_cke = 1'd0;
reg litedramcore_master_p2_odt = 1'd0;
reg litedramcore_master_p2_reset_n = 1'd0;
reg litedramcore_master_p2_act_n = 1'd1;
reg [31:0] litedramcore_master_p2_wrdata = 32'd0;
reg litedramcore_master_p2_wrdata_en = 1'd0;
reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0;
reg litedramcore_master_p2_rddata_en = 1'd0;
wire [31:0] litedramcore_master_p2_rddata;
wire litedramcore_master_p2_rddata_valid;
reg [14:0] litedramcore_master_p3_address = 15'd0;
reg [2:0] litedramcore_master_p3_bank = 3'd0;
reg litedramcore_master_p3_cas_n = 1'd1;
reg litedramcore_master_p3_cs_n = 1'd1;
reg litedramcore_master_p3_ras_n = 1'd1;
reg litedramcore_master_p3_we_n = 1'd1;
reg litedramcore_master_p3_cke = 1'd0;
reg litedramcore_master_p3_odt = 1'd0;
reg litedramcore_master_p3_reset_n = 1'd0;
reg litedramcore_master_p3_act_n = 1'd1;
reg [31:0] litedramcore_master_p3_wrdata = 32'd0;
reg litedramcore_master_p3_wrdata_en = 1'd0;
reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0;
reg litedramcore_master_p3_rddata_en = 1'd0;
wire [31:0] litedramcore_master_p3_rddata;
wire litedramcore_master_p3_rddata_valid;
reg [3:0] litedramcore_storage = 4'd0;
reg litedramcore_re = 1'd0;
reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
reg litedramcore_phaseinjector0_command_re = 1'd0;
wire litedramcore_phaseinjector0_command_issue_re;
wire litedramcore_phaseinjector0_command_issue_r;
wire litedramcore_phaseinjector0_command_issue_we;
reg litedramcore_phaseinjector0_command_issue_w = 1'd0;
reg [14:0] litedramcore_phaseinjector0_address_storage = 15'd0;
reg litedramcore_phaseinjector0_address_re = 1'd0;
reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
reg litedramcore_phaseinjector0_baddress_re = 1'd0;
reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0;
reg litedramcore_phaseinjector0_wrdata_re = 1'd0;
reg [31:0] litedramcore_phaseinjector0_status = 32'd0;
wire litedramcore_phaseinjector0_we;
reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
reg litedramcore_phaseinjector1_command_re = 1'd0;
wire litedramcore_phaseinjector1_command_issue_re;
wire litedramcore_phaseinjector1_command_issue_r;
wire litedramcore_phaseinjector1_command_issue_we;
reg litedramcore_phaseinjector1_command_issue_w = 1'd0;
reg [14:0] litedramcore_phaseinjector1_address_storage = 15'd0;
reg litedramcore_phaseinjector1_address_re = 1'd0;
reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
reg litedramcore_phaseinjector1_baddress_re = 1'd0;
reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0;
reg litedramcore_phaseinjector1_wrdata_re = 1'd0;
reg [31:0] litedramcore_phaseinjector1_status = 32'd0;
wire litedramcore_phaseinjector1_we;
reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0;
reg litedramcore_phaseinjector2_command_re = 1'd0;
wire litedramcore_phaseinjector2_command_issue_re;
wire litedramcore_phaseinjector2_command_issue_r;
wire litedramcore_phaseinjector2_command_issue_we;
reg litedramcore_phaseinjector2_command_issue_w = 1'd0;
reg [14:0] litedramcore_phaseinjector2_address_storage = 15'd0;
reg litedramcore_phaseinjector2_address_re = 1'd0;
reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0;
reg litedramcore_phaseinjector2_baddress_re = 1'd0;
reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0;
reg litedramcore_phaseinjector2_wrdata_re = 1'd0;
reg [31:0] litedramcore_phaseinjector2_status = 32'd0;
wire litedramcore_phaseinjector2_we;
reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0;
reg litedramcore_phaseinjector3_command_re = 1'd0;
wire litedramcore_phaseinjector3_command_issue_re;
wire litedramcore_phaseinjector3_command_issue_r;
wire litedramcore_phaseinjector3_command_issue_we;
reg litedramcore_phaseinjector3_command_issue_w = 1'd0;
reg [14:0] litedramcore_phaseinjector3_address_storage = 15'd0;
reg litedramcore_phaseinjector3_address_re = 1'd0;
reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0;
reg litedramcore_phaseinjector3_baddress_re = 1'd0;
reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0;
reg litedramcore_phaseinjector3_wrdata_re = 1'd0;
reg [31:0] litedramcore_phaseinjector3_status = 32'd0;
wire litedramcore_phaseinjector3_we;
wire litedramcore_interface_bank0_valid;
wire litedramcore_interface_bank0_ready;
wire litedramcore_interface_bank0_we;
wire [21:0] litedramcore_interface_bank0_addr;
wire litedramcore_interface_bank0_lock;
wire litedramcore_interface_bank0_wdata_ready;
wire litedramcore_interface_bank0_rdata_valid;
wire litedramcore_interface_bank1_valid;
wire litedramcore_interface_bank1_ready;
wire litedramcore_interface_bank1_we;
wire [21:0] litedramcore_interface_bank1_addr;
wire litedramcore_interface_bank1_lock;
wire litedramcore_interface_bank1_wdata_ready;
wire litedramcore_interface_bank1_rdata_valid;
wire litedramcore_interface_bank2_valid;
wire litedramcore_interface_bank2_ready;
wire litedramcore_interface_bank2_we;
wire [21:0] litedramcore_interface_bank2_addr;
wire litedramcore_interface_bank2_lock;
wire litedramcore_interface_bank2_wdata_ready;
wire litedramcore_interface_bank2_rdata_valid;
wire litedramcore_interface_bank3_valid;
wire litedramcore_interface_bank3_ready;
wire litedramcore_interface_bank3_we;
wire [21:0] litedramcore_interface_bank3_addr;
wire litedramcore_interface_bank3_lock;
wire litedramcore_interface_bank3_wdata_ready;
wire litedramcore_interface_bank3_rdata_valid;
wire litedramcore_interface_bank4_valid;
wire litedramcore_interface_bank4_ready;
wire litedramcore_interface_bank4_we;
wire [21:0] litedramcore_interface_bank4_addr;
wire litedramcore_interface_bank4_lock;
wire litedramcore_interface_bank4_wdata_ready;
wire litedramcore_interface_bank4_rdata_valid;
wire litedramcore_interface_bank5_valid;
wire litedramcore_interface_bank5_ready;
wire litedramcore_interface_bank5_we;
wire [21:0] litedramcore_interface_bank5_addr;
wire litedramcore_interface_bank5_lock;
wire litedramcore_interface_bank5_wdata_ready;
wire litedramcore_interface_bank5_rdata_valid;
wire litedramcore_interface_bank6_valid;
wire litedramcore_interface_bank6_ready;
wire litedramcore_interface_bank6_we;
wire [21:0] litedramcore_interface_bank6_addr;
wire litedramcore_interface_bank6_lock;
wire litedramcore_interface_bank6_wdata_ready;
wire litedramcore_interface_bank6_rdata_valid;
wire litedramcore_interface_bank7_valid;
wire litedramcore_interface_bank7_ready;
wire litedramcore_interface_bank7_we;
wire [21:0] litedramcore_interface_bank7_addr;
wire litedramcore_interface_bank7_lock;
wire litedramcore_interface_bank7_wdata_ready;
wire litedramcore_interface_bank7_rdata_valid;
reg [127:0] litedramcore_interface_wdata = 128'd0;
reg [15:0] litedramcore_interface_wdata_we = 16'd0;
wire [127:0] litedramcore_interface_rdata;
reg [14:0] litedramcore_dfi_p0_address = 15'd0;
reg [2:0] litedramcore_dfi_p0_bank = 3'd0;
reg litedramcore_dfi_p0_cas_n = 1'd1;
reg litedramcore_dfi_p0_cs_n = 1'd1;
reg litedramcore_dfi_p0_ras_n = 1'd1;
reg litedramcore_dfi_p0_we_n = 1'd1;
wire litedramcore_dfi_p0_cke;
wire litedramcore_dfi_p0_odt;
wire litedramcore_dfi_p0_reset_n;
reg litedramcore_dfi_p0_act_n = 1'd1;
wire [31:0] litedramcore_dfi_p0_wrdata;
reg litedramcore_dfi_p0_wrdata_en = 1'd0;
wire [3:0] litedramcore_dfi_p0_wrdata_mask;
reg litedramcore_dfi_p0_rddata_en = 1'd0;
wire [31:0] litedramcore_dfi_p0_rddata;
wire litedramcore_dfi_p0_rddata_valid;
reg [14:0] litedramcore_dfi_p1_address = 15'd0;
reg [2:0] litedramcore_dfi_p1_bank = 3'd0;
reg litedramcore_dfi_p1_cas_n = 1'd1;
reg litedramcore_dfi_p1_cs_n = 1'd1;
reg litedramcore_dfi_p1_ras_n = 1'd1;
reg litedramcore_dfi_p1_we_n = 1'd1;
wire litedramcore_dfi_p1_cke;
wire litedramcore_dfi_p1_odt;
wire litedramcore_dfi_p1_reset_n;
reg litedramcore_dfi_p1_act_n = 1'd1;
wire [31:0] litedramcore_dfi_p1_wrdata;
reg litedramcore_dfi_p1_wrdata_en = 1'd0;
wire [3:0] litedramcore_dfi_p1_wrdata_mask;
reg litedramcore_dfi_p1_rddata_en = 1'd0;
wire [31:0] litedramcore_dfi_p1_rddata;
wire litedramcore_dfi_p1_rddata_valid;
reg [14:0] litedramcore_dfi_p2_address = 15'd0;
reg [2:0] litedramcore_dfi_p2_bank = 3'd0;
reg litedramcore_dfi_p2_cas_n = 1'd1;
reg litedramcore_dfi_p2_cs_n = 1'd1;
reg litedramcore_dfi_p2_ras_n = 1'd1;
reg litedramcore_dfi_p2_we_n = 1'd1;
wire litedramcore_dfi_p2_cke;
wire litedramcore_dfi_p2_odt;
wire litedramcore_dfi_p2_reset_n;
reg litedramcore_dfi_p2_act_n = 1'd1;
wire [31:0] litedramcore_dfi_p2_wrdata;
reg litedramcore_dfi_p2_wrdata_en = 1'd0;
wire [3:0] litedramcore_dfi_p2_wrdata_mask;
reg litedramcore_dfi_p2_rddata_en = 1'd0;
wire [31:0] litedramcore_dfi_p2_rddata;
wire litedramcore_dfi_p2_rddata_valid;
reg [14:0] litedramcore_dfi_p3_address = 15'd0;
reg [2:0] litedramcore_dfi_p3_bank = 3'd0;
reg litedramcore_dfi_p3_cas_n = 1'd1;
reg litedramcore_dfi_p3_cs_n = 1'd1;
reg litedramcore_dfi_p3_ras_n = 1'd1;
reg litedramcore_dfi_p3_we_n = 1'd1;
wire litedramcore_dfi_p3_cke;
wire litedramcore_dfi_p3_odt;
wire litedramcore_dfi_p3_reset_n;
reg litedramcore_dfi_p3_act_n = 1'd1;
wire [31:0] litedramcore_dfi_p3_wrdata;
reg litedramcore_dfi_p3_wrdata_en = 1'd0;
wire [3:0] litedramcore_dfi_p3_wrdata_mask;
reg litedramcore_dfi_p3_rddata_en = 1'd0;
wire [31:0] litedramcore_dfi_p3_rddata;
wire litedramcore_dfi_p3_rddata_valid;
reg litedramcore_cmd_valid = 1'd0;
reg litedramcore_cmd_ready = 1'd0;
reg litedramcore_cmd_last = 1'd0;
reg [14:0] litedramcore_cmd_payload_a = 15'd0;
reg [2:0] litedramcore_cmd_payload_ba = 3'd0;
reg litedramcore_cmd_payload_cas = 1'd0;
reg litedramcore_cmd_payload_ras = 1'd0;
reg litedramcore_cmd_payload_we = 1'd0;
reg litedramcore_cmd_payload_is_read = 1'd0;
reg litedramcore_cmd_payload_is_write = 1'd0;
wire litedramcore_wants_refresh;
wire litedramcore_wants_zqcs;
wire litedramcore_timer_wait;
wire litedramcore_timer_done0;
wire [9:0] litedramcore_timer_count0;
wire litedramcore_timer_done1;
reg [9:0] litedramcore_timer_count1 = 10'd781;
wire litedramcore_postponer_req_i;
reg litedramcore_postponer_req_o = 1'd0;
reg litedramcore_postponer_count = 1'd0;
reg litedramcore_sequencer_start0 = 1'd0;
wire litedramcore_sequencer_done0;
wire litedramcore_sequencer_start1;
reg litedramcore_sequencer_done1 = 1'd0;
reg [5:0] litedramcore_sequencer_counter = 6'd0;
reg litedramcore_sequencer_count = 1'd0;
wire litedramcore_zqcs_timer_wait;
wire litedramcore_zqcs_timer_done0;
wire [26:0] litedramcore_zqcs_timer_count0;
wire litedramcore_zqcs_timer_done1;
reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999;
reg litedramcore_zqcs_executer_start = 1'd0;
reg litedramcore_zqcs_executer_done = 1'd0;
reg [4:0] litedramcore_zqcs_executer_counter = 5'd0;
wire litedramcore_bankmachine0_req_valid;
wire litedramcore_bankmachine0_req_ready;
wire litedramcore_bankmachine0_req_we;
wire [21:0] litedramcore_bankmachine0_req_addr;
wire litedramcore_bankmachine0_req_lock;
reg litedramcore_bankmachine0_req_wdata_ready = 1'd0;
reg litedramcore_bankmachine0_req_rdata_valid = 1'd0;
wire litedramcore_bankmachine0_refresh_req;
reg litedramcore_bankmachine0_refresh_gnt = 1'd0;
reg litedramcore_bankmachine0_cmd_valid = 1'd0;
reg litedramcore_bankmachine0_cmd_ready = 1'd0;
reg [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0;
wire [2:0] litedramcore_bankmachine0_cmd_payload_ba;
reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
reg litedramcore_bankmachine0_cmd_payload_we = 1'd0;
reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
reg litedramcore_bankmachine0_auto_precharge = 1'd0;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
reg [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
reg litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
wire litedramcore_bankmachine0_cmd_buffer_sink_valid;
wire litedramcore_bankmachine0_cmd_buffer_sink_ready;
wire litedramcore_bankmachine0_cmd_buffer_sink_first;
wire litedramcore_bankmachine0_cmd_buffer_sink_last;
wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
wire [21:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
reg litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
wire litedramcore_bankmachine0_cmd_buffer_source_ready;
reg litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
reg litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
reg litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
reg [21:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0;
reg [14:0] litedramcore_bankmachine0_row = 15'd0;
reg litedramcore_bankmachine0_row_opened = 1'd0;
wire litedramcore_bankmachine0_row_hit;
reg litedramcore_bankmachine0_row_open = 1'd0;
reg litedramcore_bankmachine0_row_close = 1'd0;
reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine0_twtpcon_valid;
(* dont_touch = "true" *) reg litedramcore_bankmachine0_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
wire litedramcore_bankmachine0_trccon_valid;
(* dont_touch = "true" *) reg litedramcore_bankmachine0_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
wire litedramcore_bankmachine0_trascon_valid;
(* dont_touch = "true" *) reg litedramcore_bankmachine0_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
wire litedramcore_bankmachine1_req_valid;
wire litedramcore_bankmachine1_req_ready;
wire litedramcore_bankmachine1_req_we;
wire [21:0] litedramcore_bankmachine1_req_addr;
wire litedramcore_bankmachine1_req_lock;
reg litedramcore_bankmachine1_req_wdata_ready = 1'd0;
reg litedramcore_bankmachine1_req_rdata_valid = 1'd0;
wire litedramcore_bankmachine1_refresh_req;
reg litedramcore_bankmachine1_refresh_gnt = 1'd0;
reg litedramcore_bankmachine1_cmd_valid = 1'd0;
reg litedramcore_bankmachine1_cmd_ready = 1'd0;
reg [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0;
wire [2:0] litedramcore_bankmachine1_cmd_payload_ba;
reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
reg litedramcore_bankmachine1_cmd_payload_we = 1'd0;
reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
reg litedramcore_bankmachine1_auto_precharge = 1'd0;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
reg [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
reg litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
wire litedramcore_bankmachine1_cmd_buffer_sink_valid;
wire litedramcore_bankmachine1_cmd_buffer_sink_ready;
wire litedramcore_bankmachine1_cmd_buffer_sink_first;
wire litedramcore_bankmachine1_cmd_buffer_sink_last;
wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
wire [21:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
reg litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
wire litedramcore_bankmachine1_cmd_buffer_source_ready;
reg litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
reg litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
reg litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
reg [21:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0;
reg [14:0] litedramcore_bankmachine1_row = 15'd0;
reg litedramcore_bankmachine1_row_opened = 1'd0;
wire litedramcore_bankmachine1_row_hit;
reg litedramcore_bankmachine1_row_open = 1'd0;
reg litedramcore_bankmachine1_row_close = 1'd0;
reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine1_twtpcon_valid;
(* dont_touch = "true" *) reg litedramcore_bankmachine1_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
wire litedramcore_bankmachine1_trccon_valid;
(* dont_touch = "true" *) reg litedramcore_bankmachine1_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
wire litedramcore_bankmachine1_trascon_valid;
(* dont_touch = "true" *) reg litedramcore_bankmachine1_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
wire litedramcore_bankmachine2_req_valid;
wire litedramcore_bankmachine2_req_ready;
wire litedramcore_bankmachine2_req_we;
wire [21:0] litedramcore_bankmachine2_req_addr;
wire litedramcore_bankmachine2_req_lock;
reg litedramcore_bankmachine2_req_wdata_ready = 1'd0;
reg litedramcore_bankmachine2_req_rdata_valid = 1'd0;
wire litedramcore_bankmachine2_refresh_req;
reg litedramcore_bankmachine2_refresh_gnt = 1'd0;
reg litedramcore_bankmachine2_cmd_valid = 1'd0;
reg litedramcore_bankmachine2_cmd_ready = 1'd0;
reg [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0;
wire [2:0] litedramcore_bankmachine2_cmd_payload_ba;
reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
reg litedramcore_bankmachine2_cmd_payload_we = 1'd0;
reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
reg litedramcore_bankmachine2_auto_precharge = 1'd0;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
reg [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
reg litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
wire litedramcore_bankmachine2_cmd_buffer_sink_valid;
wire litedramcore_bankmachine2_cmd_buffer_sink_ready;
wire litedramcore_bankmachine2_cmd_buffer_sink_first;
wire litedramcore_bankmachine2_cmd_buffer_sink_last;
wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
wire [21:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
reg litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
wire litedramcore_bankmachine2_cmd_buffer_source_ready;
reg litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
reg litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
reg litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
reg [21:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0;
reg [14:0] litedramcore_bankmachine2_row = 15'd0;
reg litedramcore_bankmachine2_row_opened = 1'd0;
wire litedramcore_bankmachine2_row_hit;
reg litedramcore_bankmachine2_row_open = 1'd0;
reg litedramcore_bankmachine2_row_close = 1'd0;
reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine2_twtpcon_valid;
(* dont_touch = "true" *) reg litedramcore_bankmachine2_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
wire litedramcore_bankmachine2_trccon_valid;
(* dont_touch = "true" *) reg litedramcore_bankmachine2_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
wire litedramcore_bankmachine2_trascon_valid;
(* dont_touch = "true" *) reg litedramcore_bankmachine2_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
wire litedramcore_bankmachine3_req_valid;
wire litedramcore_bankmachine3_req_ready;
wire litedramcore_bankmachine3_req_we;
wire [21:0] litedramcore_bankmachine3_req_addr;
wire litedramcore_bankmachine3_req_lock;
reg litedramcore_bankmachine3_req_wdata_ready = 1'd0;
reg litedramcore_bankmachine3_req_rdata_valid = 1'd0;
wire litedramcore_bankmachine3_refresh_req;
reg litedramcore_bankmachine3_refresh_gnt = 1'd0;
reg litedramcore_bankmachine3_cmd_valid = 1'd0;
reg litedramcore_bankmachine3_cmd_ready = 1'd0;
reg [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0;
wire [2:0] litedramcore_bankmachine3_cmd_payload_ba;
reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
reg litedramcore_bankmachine3_cmd_payload_we = 1'd0;
reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
reg litedramcore_bankmachine3_auto_precharge = 1'd0;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
reg [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
reg litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
wire litedramcore_bankmachine3_cmd_buffer_sink_valid;
wire litedramcore_bankmachine3_cmd_buffer_sink_ready;
wire litedramcore_bankmachine3_cmd_buffer_sink_first;
wire litedramcore_bankmachine3_cmd_buffer_sink_last;
wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
wire [21:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
reg litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
wire litedramcore_bankmachine3_cmd_buffer_source_ready;
reg litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
reg litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
reg litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
reg [21:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0;
reg [14:0] litedramcore_bankmachine3_row = 15'd0;
reg litedramcore_bankmachine3_row_opened = 1'd0;
wire litedramcore_bankmachine3_row_hit;
reg litedramcore_bankmachine3_row_open = 1'd0;
reg litedramcore_bankmachine3_row_close = 1'd0;
reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine3_twtpcon_valid;
(* dont_touch = "true" *) reg litedramcore_bankmachine3_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
wire litedramcore_bankmachine3_trccon_valid;
(* dont_touch = "true" *) reg litedramcore_bankmachine3_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
wire litedramcore_bankmachine3_trascon_valid;
(* dont_touch = "true" *) reg litedramcore_bankmachine3_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
wire litedramcore_bankmachine4_req_valid;
wire litedramcore_bankmachine4_req_ready;
wire litedramcore_bankmachine4_req_we;
wire [21:0] litedramcore_bankmachine4_req_addr;
wire litedramcore_bankmachine4_req_lock;
reg litedramcore_bankmachine4_req_wdata_ready = 1'd0;
reg litedramcore_bankmachine4_req_rdata_valid = 1'd0;
wire litedramcore_bankmachine4_refresh_req;
reg litedramcore_bankmachine4_refresh_gnt = 1'd0;
reg litedramcore_bankmachine4_cmd_valid = 1'd0;
reg litedramcore_bankmachine4_cmd_ready = 1'd0;
reg [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0;
wire [2:0] litedramcore_bankmachine4_cmd_payload_ba;
reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
reg litedramcore_bankmachine4_cmd_payload_we = 1'd0;
reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
reg litedramcore_bankmachine4_auto_precharge = 1'd0;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
reg [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
reg litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
wire litedramcore_bankmachine4_cmd_buffer_sink_valid;
wire litedramcore_bankmachine4_cmd_buffer_sink_ready;
wire litedramcore_bankmachine4_cmd_buffer_sink_first;
wire litedramcore_bankmachine4_cmd_buffer_sink_last;
wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
wire [21:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
reg litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
wire litedramcore_bankmachine4_cmd_buffer_source_ready;
reg litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
reg litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
reg litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
reg [21:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0;
reg [14:0] litedramcore_bankmachine4_row = 15'd0;
reg litedramcore_bankmachine4_row_opened = 1'd0;
wire litedramcore_bankmachine4_row_hit;
reg litedramcore_bankmachine4_row_open = 1'd0;
reg litedramcore_bankmachine4_row_close = 1'd0;
reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine4_twtpcon_valid;
(* dont_touch = "true" *) reg litedramcore_bankmachine4_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
wire litedramcore_bankmachine4_trccon_valid;
(* dont_touch = "true" *) reg litedramcore_bankmachine4_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
wire litedramcore_bankmachine4_trascon_valid;
(* dont_touch = "true" *) reg litedramcore_bankmachine4_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
wire litedramcore_bankmachine5_req_valid;
wire litedramcore_bankmachine5_req_ready;
wire litedramcore_bankmachine5_req_we;
wire [21:0] litedramcore_bankmachine5_req_addr;
wire litedramcore_bankmachine5_req_lock;
reg litedramcore_bankmachine5_req_wdata_ready = 1'd0;
reg litedramcore_bankmachine5_req_rdata_valid = 1'd0;
wire litedramcore_bankmachine5_refresh_req;
reg litedramcore_bankmachine5_refresh_gnt = 1'd0;
reg litedramcore_bankmachine5_cmd_valid = 1'd0;
reg litedramcore_bankmachine5_cmd_ready = 1'd0;
reg [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0;
wire [2:0] litedramcore_bankmachine5_cmd_payload_ba;
reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
reg litedramcore_bankmachine5_cmd_payload_we = 1'd0;
reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
reg litedramcore_bankmachine5_auto_precharge = 1'd0;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
reg [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
reg litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
wire litedramcore_bankmachine5_cmd_buffer_sink_valid;
wire litedramcore_bankmachine5_cmd_buffer_sink_ready;
wire litedramcore_bankmachine5_cmd_buffer_sink_first;
wire litedramcore_bankmachine5_cmd_buffer_sink_last;
wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
wire [21:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
reg litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
wire litedramcore_bankmachine5_cmd_buffer_source_ready;
reg litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
reg litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
reg litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
reg [21:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0;
reg [14:0] litedramcore_bankmachine5_row = 15'd0;
reg litedramcore_bankmachine5_row_opened = 1'd0;
wire litedramcore_bankmachine5_row_hit;
reg litedramcore_bankmachine5_row_open = 1'd0;
reg litedramcore_bankmachine5_row_close = 1'd0;
reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine5_twtpcon_valid;
(* dont_touch = "true" *) reg litedramcore_bankmachine5_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
wire litedramcore_bankmachine5_trccon_valid;
(* dont_touch = "true" *) reg litedramcore_bankmachine5_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
wire litedramcore_bankmachine5_trascon_valid;
(* dont_touch = "true" *) reg litedramcore_bankmachine5_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
wire litedramcore_bankmachine6_req_valid;
wire litedramcore_bankmachine6_req_ready;
wire litedramcore_bankmachine6_req_we;
wire [21:0] litedramcore_bankmachine6_req_addr;
wire litedramcore_bankmachine6_req_lock;
reg litedramcore_bankmachine6_req_wdata_ready = 1'd0;
reg litedramcore_bankmachine6_req_rdata_valid = 1'd0;
wire litedramcore_bankmachine6_refresh_req;
reg litedramcore_bankmachine6_refresh_gnt = 1'd0;
reg litedramcore_bankmachine6_cmd_valid = 1'd0;
reg litedramcore_bankmachine6_cmd_ready = 1'd0;
reg [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0;
wire [2:0] litedramcore_bankmachine6_cmd_payload_ba;
reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
reg litedramcore_bankmachine6_cmd_payload_we = 1'd0;
reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
reg litedramcore_bankmachine6_auto_precharge = 1'd0;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
reg [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
reg litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
wire litedramcore_bankmachine6_cmd_buffer_sink_valid;
wire litedramcore_bankmachine6_cmd_buffer_sink_ready;
wire litedramcore_bankmachine6_cmd_buffer_sink_first;
wire litedramcore_bankmachine6_cmd_buffer_sink_last;
wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
wire [21:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
reg litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
wire litedramcore_bankmachine6_cmd_buffer_source_ready;
reg litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
reg litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
reg litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
reg [21:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0;
reg [14:0] litedramcore_bankmachine6_row = 15'd0;
reg litedramcore_bankmachine6_row_opened = 1'd0;
wire litedramcore_bankmachine6_row_hit;
reg litedramcore_bankmachine6_row_open = 1'd0;
reg litedramcore_bankmachine6_row_close = 1'd0;
reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine6_twtpcon_valid;
(* dont_touch = "true" *) reg litedramcore_bankmachine6_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
wire litedramcore_bankmachine6_trccon_valid;
(* dont_touch = "true" *) reg litedramcore_bankmachine6_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
wire litedramcore_bankmachine6_trascon_valid;
(* dont_touch = "true" *) reg litedramcore_bankmachine6_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
wire litedramcore_bankmachine7_req_valid;
wire litedramcore_bankmachine7_req_ready;
wire litedramcore_bankmachine7_req_we;
wire [21:0] litedramcore_bankmachine7_req_addr;
wire litedramcore_bankmachine7_req_lock;
reg litedramcore_bankmachine7_req_wdata_ready = 1'd0;
reg litedramcore_bankmachine7_req_rdata_valid = 1'd0;
wire litedramcore_bankmachine7_refresh_req;
reg litedramcore_bankmachine7_refresh_gnt = 1'd0;
reg litedramcore_bankmachine7_cmd_valid = 1'd0;
reg litedramcore_bankmachine7_cmd_ready = 1'd0;
reg [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0;
wire [2:0] litedramcore_bankmachine7_cmd_payload_ba;
reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
reg litedramcore_bankmachine7_cmd_payload_we = 1'd0;
reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
reg litedramcore_bankmachine7_auto_precharge = 1'd0;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
reg [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
reg litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
wire litedramcore_bankmachine7_cmd_buffer_sink_valid;
wire litedramcore_bankmachine7_cmd_buffer_sink_ready;
wire litedramcore_bankmachine7_cmd_buffer_sink_first;
wire litedramcore_bankmachine7_cmd_buffer_sink_last;
wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
wire [21:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
reg litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
wire litedramcore_bankmachine7_cmd_buffer_source_ready;
reg litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
reg litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
reg litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
reg [21:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0;
reg [14:0] litedramcore_bankmachine7_row = 15'd0;
reg litedramcore_bankmachine7_row_opened = 1'd0;
wire litedramcore_bankmachine7_row_hit;
reg litedramcore_bankmachine7_row_open = 1'd0;
reg litedramcore_bankmachine7_row_close = 1'd0;
reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine7_twtpcon_valid;
(* dont_touch = "true" *) reg litedramcore_bankmachine7_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
wire litedramcore_bankmachine7_trccon_valid;
(* dont_touch = "true" *) reg litedramcore_bankmachine7_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
wire litedramcore_bankmachine7_trascon_valid;
(* dont_touch = "true" *) reg litedramcore_bankmachine7_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
wire litedramcore_ras_allowed;
wire litedramcore_cas_allowed;
reg litedramcore_choose_cmd_want_reads = 1'd0;
reg litedramcore_choose_cmd_want_writes = 1'd0;
reg litedramcore_choose_cmd_want_cmds = 1'd0;
reg litedramcore_choose_cmd_want_activates = 1'd0;
wire litedramcore_choose_cmd_cmd_valid;
reg litedramcore_choose_cmd_cmd_ready = 1'd0;
wire [14:0] litedramcore_choose_cmd_cmd_payload_a;
wire [2:0] litedramcore_choose_cmd_cmd_payload_ba;
reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
reg litedramcore_choose_cmd_cmd_payload_we = 1'd0;
wire litedramcore_choose_cmd_cmd_payload_is_cmd;
wire litedramcore_choose_cmd_cmd_payload_is_read;
wire litedramcore_choose_cmd_cmd_payload_is_write;
reg [7:0] litedramcore_choose_cmd_valids = 8'd0;
wire [7:0] litedramcore_choose_cmd_request;
reg [2:0] litedramcore_choose_cmd_grant = 3'd0;
wire litedramcore_choose_cmd_ce;
reg litedramcore_choose_req_want_reads = 1'd0;
reg litedramcore_choose_req_want_writes = 1'd0;
reg litedramcore_choose_req_want_cmds = 1'd0;
reg litedramcore_choose_req_want_activates = 1'd0;
wire litedramcore_choose_req_cmd_valid;
reg litedramcore_choose_req_cmd_ready = 1'd0;
wire [14:0] litedramcore_choose_req_cmd_payload_a;
wire [2:0] litedramcore_choose_req_cmd_payload_ba;
reg litedramcore_choose_req_cmd_payload_cas = 1'd0;
reg litedramcore_choose_req_cmd_payload_ras = 1'd0;
reg litedramcore_choose_req_cmd_payload_we = 1'd0;
wire litedramcore_choose_req_cmd_payload_is_cmd;
wire litedramcore_choose_req_cmd_payload_is_read;
wire litedramcore_choose_req_cmd_payload_is_write;
reg [7:0] litedramcore_choose_req_valids = 8'd0;
wire [7:0] litedramcore_choose_req_request;
reg [2:0] litedramcore_choose_req_grant = 3'd0;
wire litedramcore_choose_req_ce;
reg [14:0] litedramcore_nop_a = 15'd0;
reg [2:0] litedramcore_nop_ba = 3'd0;
reg [1:0] litedramcore_steerer_sel0 = 2'd0;
reg [1:0] litedramcore_steerer_sel1 = 2'd0;
reg [1:0] litedramcore_steerer_sel2 = 2'd0;
reg [1:0] litedramcore_steerer_sel3 = 2'd0;
reg litedramcore_steerer0 = 1'd1;
reg litedramcore_steerer1 = 1'd1;
reg litedramcore_steerer2 = 1'd1;
reg litedramcore_steerer3 = 1'd1;
reg litedramcore_steerer4 = 1'd1;
reg litedramcore_steerer5 = 1'd1;
reg litedramcore_steerer6 = 1'd1;
reg litedramcore_steerer7 = 1'd1;
wire litedramcore_trrdcon_valid;
(* dont_touch = "true" *) reg litedramcore_trrdcon_ready = 1'd0;
reg litedramcore_trrdcon_count = 1'd0;
wire litedramcore_tfawcon_valid;
(* dont_touch = "true" *) reg litedramcore_tfawcon_ready = 1'd1;
wire [2:0] litedramcore_tfawcon_count;
reg [4:0] litedramcore_tfawcon_window = 5'd0;
wire litedramcore_tccdcon_valid;
(* dont_touch = "true" *) reg litedramcore_tccdcon_ready = 1'd0;
reg litedramcore_tccdcon_count = 1'd0;
wire litedramcore_twtrcon_valid;
(* dont_touch = "true" *) reg litedramcore_twtrcon_ready = 1'd0;
reg [2:0] litedramcore_twtrcon_count = 3'd0;
wire litedramcore_read_available;
wire litedramcore_write_available;
reg litedramcore_en0 = 1'd0;
wire litedramcore_max_time0;
reg [4:0] litedramcore_time0 = 5'd0;
reg litedramcore_en1 = 1'd0;
wire litedramcore_max_time1;
reg [3:0] litedramcore_time1 = 4'd0;
wire litedramcore_go_to_refresh;
reg init_done_storage = 1'd0;
reg init_done_re = 1'd0;
reg init_error_storage = 1'd0;
reg init_error_re = 1'd0;
wire [29:0] wb_bus_adr;
wire [31:0] wb_bus_dat_w;
wire [31:0] wb_bus_dat_r;
wire [3:0] wb_bus_sel;
wire wb_bus_cyc;
wire wb_bus_stb;
wire wb_bus_ack;
wire wb_bus_we;
wire [2:0] wb_bus_cti;
wire [1:0] wb_bus_bte;
wire wb_bus_err;
wire user_port_cmd_valid;
wire user_port_cmd_ready;
wire user_port_cmd_payload_we;
wire [24:0] user_port_cmd_payload_addr;
wire user_port_wdata_valid;
wire user_port_wdata_ready;
wire [127:0] user_port_wdata_payload_data;
wire [15:0] user_port_wdata_payload_we;
wire user_port_rdata_valid;
wire user_port_rdata_ready;
wire [127:0] user_port_rdata_payload_data;
reg state = 1'd0;
reg next_state = 1'd0;
wire pll_fb0;
wire pll_fb1;
reg [1:0] refresher_state = 2'd0;
reg [1:0] refresher_next_state = 2'd0;
reg [3:0] bankmachine0_state = 4'd0;
reg [3:0] bankmachine0_next_state = 4'd0;
reg [3:0] bankmachine1_state = 4'd0;
reg [3:0] bankmachine1_next_state = 4'd0;
reg [3:0] bankmachine2_state = 4'd0;
reg [3:0] bankmachine2_next_state = 4'd0;
reg [3:0] bankmachine3_state = 4'd0;
reg [3:0] bankmachine3_next_state = 4'd0;
reg [3:0] bankmachine4_state = 4'd0;
reg [3:0] bankmachine4_next_state = 4'd0;
reg [3:0] bankmachine5_state = 4'd0;
reg [3:0] bankmachine5_next_state = 4'd0;
reg [3:0] bankmachine6_state = 4'd0;
reg [3:0] bankmachine6_next_state = 4'd0;
reg [3:0] bankmachine7_state = 4'd0;
reg [3:0] bankmachine7_next_state = 4'd0;
reg [3:0] multiplexer_state = 4'd0;
reg [3:0] multiplexer_next_state = 4'd0;
wire roundrobin0_request;
wire roundrobin0_grant;
wire roundrobin0_ce;
wire roundrobin1_request;
wire roundrobin1_grant;
wire roundrobin1_ce;
wire roundrobin2_request;
wire roundrobin2_grant;
wire roundrobin2_ce;
wire roundrobin3_request;
wire roundrobin3_grant;
wire roundrobin3_ce;
wire roundrobin4_request;
wire roundrobin4_grant;
wire roundrobin4_ce;
wire roundrobin5_request;
wire roundrobin5_grant;
wire roundrobin5_ce;
wire roundrobin6_request;
wire roundrobin6_grant;
wire roundrobin6_ce;
wire roundrobin7_request;
wire roundrobin7_grant;
wire roundrobin7_ce;
reg locked0 = 1'd0;
reg locked1 = 1'd0;
reg locked2 = 1'd0;
reg locked3 = 1'd0;
reg locked4 = 1'd0;
reg locked5 = 1'd0;
reg locked6 = 1'd0;
reg locked7 = 1'd0;
reg new_master_wdata_ready0 = 1'd0;
reg new_master_wdata_ready1 = 1'd0;
reg new_master_wdata_ready2 = 1'd0;
reg new_master_rdata_valid0 = 1'd0;
reg new_master_rdata_valid1 = 1'd0;
reg new_master_rdata_valid2 = 1'd0;
reg new_master_rdata_valid3 = 1'd0;
reg new_master_rdata_valid4 = 1'd0;
reg new_master_rdata_valid5 = 1'd0;
reg new_master_rdata_valid6 = 1'd0;
reg new_master_rdata_valid7 = 1'd0;
reg new_master_rdata_valid8 = 1'd0;
wire [13:0] interface0_bank_bus_adr;
wire interface0_bank_bus_we;
wire [31:0] interface0_bank_bus_dat_w;
reg [31:0] interface0_bank_bus_dat_r = 32'd0;
wire csrbank0_init_done0_re;
wire csrbank0_init_done0_r;
wire csrbank0_init_done0_we;
wire csrbank0_init_done0_w;
wire csrbank0_init_error0_re;
wire csrbank0_init_error0_r;
wire csrbank0_init_error0_we;
wire csrbank0_init_error0_w;
reg csrbank0_sel = 1'd0;
wire [13:0] interface1_bank_bus_adr;
wire interface1_bank_bus_we;
wire [31:0] interface1_bank_bus_dat_w;
reg [31:0] interface1_bank_bus_dat_r = 32'd0;
wire csrbank1_half_sys8x_taps0_re;
wire [4:0] csrbank1_half_sys8x_taps0_r;
wire csrbank1_half_sys8x_taps0_we;
wire [4:0] csrbank1_half_sys8x_taps0_w;
wire csrbank1_wlevel_en0_re;
wire csrbank1_wlevel_en0_r;
wire csrbank1_wlevel_en0_we;
wire csrbank1_wlevel_en0_w;
wire csrbank1_dly_sel0_re;
wire [1:0] csrbank1_dly_sel0_r;
wire csrbank1_dly_sel0_we;
wire [1:0] csrbank1_dly_sel0_w;
reg csrbank1_sel = 1'd0;
wire [13:0] interface2_bank_bus_adr;
wire interface2_bank_bus_we;
wire [31:0] interface2_bank_bus_dat_w;
reg [31:0] interface2_bank_bus_dat_r = 32'd0;
wire csrbank2_dfii_control0_re;
wire [3:0] csrbank2_dfii_control0_r;
wire csrbank2_dfii_control0_we;
wire [3:0] csrbank2_dfii_control0_w;
wire csrbank2_dfii_pi0_command0_re;
wire [5:0] csrbank2_dfii_pi0_command0_r;
wire csrbank2_dfii_pi0_command0_we;
wire [5:0] csrbank2_dfii_pi0_command0_w;
wire csrbank2_dfii_pi0_address0_re;
wire [14:0] csrbank2_dfii_pi0_address0_r;
wire csrbank2_dfii_pi0_address0_we;
wire [14:0] csrbank2_dfii_pi0_address0_w;
wire csrbank2_dfii_pi0_baddress0_re;
wire [2:0] csrbank2_dfii_pi0_baddress0_r;
wire csrbank2_dfii_pi0_baddress0_we;
wire [2:0] csrbank2_dfii_pi0_baddress0_w;
wire csrbank2_dfii_pi0_wrdata0_re;
wire [31:0] csrbank2_dfii_pi0_wrdata0_r;
wire csrbank2_dfii_pi0_wrdata0_we;
wire [31:0] csrbank2_dfii_pi0_wrdata0_w;
wire csrbank2_dfii_pi0_rddata_re;
wire [31:0] csrbank2_dfii_pi0_rddata_r;
wire csrbank2_dfii_pi0_rddata_we;
wire [31:0] csrbank2_dfii_pi0_rddata_w;
wire csrbank2_dfii_pi1_command0_re;
wire [5:0] csrbank2_dfii_pi1_command0_r;
wire csrbank2_dfii_pi1_command0_we;
wire [5:0] csrbank2_dfii_pi1_command0_w;
wire csrbank2_dfii_pi1_address0_re;
wire [14:0] csrbank2_dfii_pi1_address0_r;
wire csrbank2_dfii_pi1_address0_we;
wire [14:0] csrbank2_dfii_pi1_address0_w;
wire csrbank2_dfii_pi1_baddress0_re;
wire [2:0] csrbank2_dfii_pi1_baddress0_r;
wire csrbank2_dfii_pi1_baddress0_we;
wire [2:0] csrbank2_dfii_pi1_baddress0_w;
wire csrbank2_dfii_pi1_wrdata0_re;
wire [31:0] csrbank2_dfii_pi1_wrdata0_r;
wire csrbank2_dfii_pi1_wrdata0_we;
wire [31:0] csrbank2_dfii_pi1_wrdata0_w;
wire csrbank2_dfii_pi1_rddata_re;
wire [31:0] csrbank2_dfii_pi1_rddata_r;
wire csrbank2_dfii_pi1_rddata_we;
wire [31:0] csrbank2_dfii_pi1_rddata_w;
wire csrbank2_dfii_pi2_command0_re;
wire [5:0] csrbank2_dfii_pi2_command0_r;
wire csrbank2_dfii_pi2_command0_we;
wire [5:0] csrbank2_dfii_pi2_command0_w;
wire csrbank2_dfii_pi2_address0_re;
wire [14:0] csrbank2_dfii_pi2_address0_r;
wire csrbank2_dfii_pi2_address0_we;
wire [14:0] csrbank2_dfii_pi2_address0_w;
wire csrbank2_dfii_pi2_baddress0_re;
wire [2:0] csrbank2_dfii_pi2_baddress0_r;
wire csrbank2_dfii_pi2_baddress0_we;
wire [2:0] csrbank2_dfii_pi2_baddress0_w;
wire csrbank2_dfii_pi2_wrdata0_re;
wire [31:0] csrbank2_dfii_pi2_wrdata0_r;
wire csrbank2_dfii_pi2_wrdata0_we;
wire [31:0] csrbank2_dfii_pi2_wrdata0_w;
wire csrbank2_dfii_pi2_rddata_re;
wire [31:0] csrbank2_dfii_pi2_rddata_r;
wire csrbank2_dfii_pi2_rddata_we;
wire [31:0] csrbank2_dfii_pi2_rddata_w;
wire csrbank2_dfii_pi3_command0_re;
wire [5:0] csrbank2_dfii_pi3_command0_r;
wire csrbank2_dfii_pi3_command0_we;
wire [5:0] csrbank2_dfii_pi3_command0_w;
wire csrbank2_dfii_pi3_address0_re;
wire [14:0] csrbank2_dfii_pi3_address0_r;
wire csrbank2_dfii_pi3_address0_we;
wire [14:0] csrbank2_dfii_pi3_address0_w;
wire csrbank2_dfii_pi3_baddress0_re;
wire [2:0] csrbank2_dfii_pi3_baddress0_r;
wire csrbank2_dfii_pi3_baddress0_we;
wire [2:0] csrbank2_dfii_pi3_baddress0_w;
wire csrbank2_dfii_pi3_wrdata0_re;
wire [31:0] csrbank2_dfii_pi3_wrdata0_r;
wire csrbank2_dfii_pi3_wrdata0_we;
wire [31:0] csrbank2_dfii_pi3_wrdata0_w;
wire csrbank2_dfii_pi3_rddata_re;
wire [31:0] csrbank2_dfii_pi3_rddata_r;
wire csrbank2_dfii_pi3_rddata_we;
wire [31:0] csrbank2_dfii_pi3_rddata_w;
reg csrbank2_sel = 1'd0;
wire [13:0] adr;
wire we;
wire [31:0] dat_w;
wire [31:0] dat_r;
reg rhs_array_muxed0 = 1'd0;
reg [14:0] rhs_array_muxed1 = 15'd0;
reg [2:0] rhs_array_muxed2 = 3'd0;
reg rhs_array_muxed3 = 1'd0;
reg rhs_array_muxed4 = 1'd0;
reg rhs_array_muxed5 = 1'd0;
reg t_array_muxed0 = 1'd0;
reg t_array_muxed1 = 1'd0;
reg t_array_muxed2 = 1'd0;
reg rhs_array_muxed6 = 1'd0;
reg [14:0] rhs_array_muxed7 = 15'd0;
reg [2:0] rhs_array_muxed8 = 3'd0;
reg rhs_array_muxed9 = 1'd0;
reg rhs_array_muxed10 = 1'd0;
reg rhs_array_muxed11 = 1'd0;
reg t_array_muxed3 = 1'd0;
reg t_array_muxed4 = 1'd0;
reg t_array_muxed5 = 1'd0;
reg [21:0] rhs_array_muxed12 = 22'd0;
reg rhs_array_muxed13 = 1'd0;
reg rhs_array_muxed14 = 1'd0;
reg [21:0] rhs_array_muxed15 = 22'd0;
reg rhs_array_muxed16 = 1'd0;
reg rhs_array_muxed17 = 1'd0;
reg [21:0] rhs_array_muxed18 = 22'd0;
reg rhs_array_muxed19 = 1'd0;
reg rhs_array_muxed20 = 1'd0;
reg [21:0] rhs_array_muxed21 = 22'd0;
reg rhs_array_muxed22 = 1'd0;
reg rhs_array_muxed23 = 1'd0;
reg [21:0] rhs_array_muxed24 = 22'd0;
reg rhs_array_muxed25 = 1'd0;
reg rhs_array_muxed26 = 1'd0;
reg [21:0] rhs_array_muxed27 = 22'd0;
reg rhs_array_muxed28 = 1'd0;
reg rhs_array_muxed29 = 1'd0;
reg [21:0] rhs_array_muxed30 = 22'd0;
reg rhs_array_muxed31 = 1'd0;
reg rhs_array_muxed32 = 1'd0;
reg [21:0] rhs_array_muxed33 = 22'd0;
reg rhs_array_muxed34 = 1'd0;
reg rhs_array_muxed35 = 1'd0;
reg [2:0] array_muxed0 = 3'd0;
reg [14:0] array_muxed1 = 15'd0;
reg array_muxed2 = 1'd0;
reg array_muxed3 = 1'd0;
reg array_muxed4 = 1'd0;
reg array_muxed5 = 1'd0;
reg array_muxed6 = 1'd0;
reg [2:0] array_muxed7 = 3'd0;
reg [14:0] array_muxed8 = 15'd0;
reg array_muxed9 = 1'd0;
reg array_muxed10 = 1'd0;
reg array_muxed11 = 1'd0;
reg array_muxed12 = 1'd0;
reg array_muxed13 = 1'd0;
reg [2:0] array_muxed14 = 3'd0;
reg [14:0] array_muxed15 = 15'd0;
reg array_muxed16 = 1'd0;
reg array_muxed17 = 1'd0;
reg array_muxed18 = 1'd0;
reg array_muxed19 = 1'd0;
reg array_muxed20 = 1'd0;
reg [2:0] array_muxed21 = 3'd0;
reg [14:0] array_muxed22 = 15'd0;
reg array_muxed23 = 1'd0;
reg array_muxed24 = 1'd0;
reg array_muxed25 = 1'd0;
reg array_muxed26 = 1'd0;
reg array_muxed27 = 1'd0;
wire xilinxasyncresetsynchronizerimpl0;
wire xilinxasyncresetsynchronizerimpl0_rst_meta;
wire xilinxasyncresetsynchronizerimpl1;
wire xilinxasyncresetsynchronizerimpl1_rst_meta;
wire xilinxasyncresetsynchronizerimpl1_expr;
wire xilinxasyncresetsynchronizerimpl2;
wire xilinxasyncresetsynchronizerimpl2_rst_meta;
wire xilinxasyncresetsynchronizerimpl2_expr;
wire xilinxasyncresetsynchronizerimpl3;
wire xilinxasyncresetsynchronizerimpl3_rst_meta;

// synthesis translate_off
reg dummy_s;
initial dummy_s <= 1'd0;
// synthesis translate_on
assign init_done = init_done_storage;
assign init_error = init_error_storage;
assign wb_bus_adr = wb_ctrl_adr;
assign wb_bus_dat_w = wb_ctrl_dat_w;
assign wb_ctrl_dat_r = wb_bus_dat_r;
assign wb_bus_sel = wb_ctrl_sel;
assign wb_bus_cyc = wb_ctrl_cyc;
assign wb_bus_stb = wb_ctrl_stb;
assign wb_ctrl_ack = wb_bus_ack;
assign wb_bus_we = wb_ctrl_we;
assign wb_bus_cti = wb_ctrl_cti;
assign wb_bus_bte = wb_ctrl_bte;
assign wb_ctrl_err = wb_bus_err;
assign user_clk = sys_clk;
assign user_rst = sys_rst;
assign user_port_cmd_valid = user_port_native_0_cmd_valid;
assign user_port_native_0_cmd_ready = user_port_cmd_ready;
assign user_port_cmd_payload_we = user_port_native_0_cmd_we;
assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
assign user_port_wdata_valid = user_port_native_0_wdata_valid;
assign user_port_native_0_wdata_ready = user_port_wdata_ready;
assign user_port_wdata_payload_we = user_port_native_0_wdata_we;
assign user_port_wdata_payload_data = user_port_native_0_wdata_data;
assign user_port_native_0_rdata_valid = user_port_rdata_valid;
assign user_port_rdata_ready = user_port_native_0_rdata_ready;
assign user_port_native_0_rdata_data = user_port_rdata_payload_data;
assign litedramcore_dat_w = litedramcore_wishbone_dat_w;
assign litedramcore_wishbone_dat_r = litedramcore_dat_r;

// synthesis translate_off
reg dummy_d;
// synthesis translate_on
always @(*) begin
	next_state <= 1'd0;
	next_state <= state;
	case (state)
		1'd1: begin
			next_state <= 1'd0;
		end
		default: begin
			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
				next_state <= 1'd1;
			end
		end
	endcase
// synthesis translate_off
	dummy_d = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_1;
// synthesis translate_on
always @(*) begin
	litedramcore_adr <= 14'd0;
	case (state)
		1'd1: begin
		end
		default: begin
			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
				litedramcore_adr <= litedramcore_wishbone_adr;
			end
		end
	endcase
// synthesis translate_off
	dummy_d_1 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_2;
// synthesis translate_on
always @(*) begin
	litedramcore_we <= 1'd0;
	case (state)
		1'd1: begin
		end
		default: begin
			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
				litedramcore_we <= litedramcore_wishbone_we;
			end
		end
	endcase
// synthesis translate_off
	dummy_d_2 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_3;
// synthesis translate_on
always @(*) begin
	litedramcore_wishbone_ack <= 1'd0;
	case (state)
		1'd1: begin
			litedramcore_wishbone_ack <= 1'd1;
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_3 = dummy_s;
// synthesis translate_on
end
assign sys_pll_reset = rst;
assign pll_locked = sys_pll_locked;
assign iodelay_pll_reset = rst;
assign s7pll0_clkin = clk;
assign sys_clk = s7pll0_clkout_buf0;
assign sys4x_clk = s7pll0_clkout_buf1;
assign sys4x_dqs_clk = s7pll0_clkout_buf2;
assign s7pll1_clkin = clk;
assign iodelay_clk = s7pll1_clkout_buf;
assign a7ddrphy_bitslip0_i = a7ddrphy_dq_i_data0;

// synthesis translate_off
reg dummy_d_4;
// synthesis translate_on
always @(*) begin
	a7ddrphy_dfi_p0_rddata <= 32'd0;
	a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip0_o[0];
	a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip0_o[1];
	a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip1_o[0];
	a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip1_o[1];
	a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip2_o[0];
	a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip2_o[1];
	a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip3_o[0];
	a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip3_o[1];
	a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip4_o[0];
	a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip4_o[1];
	a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip5_o[0];
	a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip5_o[1];
	a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip6_o[0];
	a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip6_o[1];
	a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip7_o[0];
	a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip7_o[1];
	a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip8_o[0];
	a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip8_o[1];
	a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip9_o[0];
	a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip9_o[1];
	a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip10_o[0];
	a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip10_o[1];
	a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip11_o[0];
	a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip11_o[1];
	a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip12_o[0];
	a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip12_o[1];
	a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip13_o[0];
	a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip13_o[1];
	a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip14_o[0];
	a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip14_o[1];
	a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip15_o[0];
	a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip15_o[1];
// synthesis translate_off
	dummy_d_4 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_5;
// synthesis translate_on
always @(*) begin
	a7ddrphy_dfi_p1_rddata <= 32'd0;
	a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip0_o[2];
	a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip0_o[3];
	a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip1_o[2];
	a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip1_o[3];
	a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip2_o[2];
	a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip2_o[3];
	a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip3_o[2];
	a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip3_o[3];
	a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip4_o[2];
	a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip4_o[3];
	a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip5_o[2];
	a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip5_o[3];
	a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip6_o[2];
	a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip6_o[3];
	a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip7_o[2];
	a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip7_o[3];
	a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip8_o[2];
	a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip8_o[3];
	a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip9_o[2];
	a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip9_o[3];
	a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip10_o[2];
	a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip10_o[3];
	a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip11_o[2];
	a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip11_o[3];
	a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip12_o[2];
	a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip12_o[3];
	a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip13_o[2];
	a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip13_o[3];
	a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip14_o[2];
	a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip14_o[3];
	a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip15_o[2];
	a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip15_o[3];
// synthesis translate_off
	dummy_d_5 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_6;
// synthesis translate_on
always @(*) begin
	a7ddrphy_dfi_p2_rddata <= 32'd0;
	a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip0_o[4];
	a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip0_o[5];
	a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip1_o[4];
	a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip1_o[5];
	a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip2_o[4];
	a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip2_o[5];
	a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip3_o[4];
	a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip3_o[5];
	a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip4_o[4];
	a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip4_o[5];
	a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip5_o[4];
	a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip5_o[5];
	a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip6_o[4];
	a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip6_o[5];
	a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip7_o[4];
	a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip7_o[5];
	a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip8_o[4];
	a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip8_o[5];
	a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip9_o[4];
	a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip9_o[5];
	a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip10_o[4];
	a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip10_o[5];
	a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip11_o[4];
	a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip11_o[5];
	a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip12_o[4];
	a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip12_o[5];
	a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip13_o[4];
	a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip13_o[5];
	a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip14_o[4];
	a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip14_o[5];
	a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip15_o[4];
	a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip15_o[5];
// synthesis translate_off
	dummy_d_6 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_7;
// synthesis translate_on
always @(*) begin
	a7ddrphy_dfi_p3_rddata <= 32'd0;
	a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip0_o[6];
	a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip0_o[7];
	a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip1_o[6];
	a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip1_o[7];
	a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip2_o[6];
	a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip2_o[7];
	a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip3_o[6];
	a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip3_o[7];
	a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip4_o[6];
	a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip4_o[7];
	a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip5_o[6];
	a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip5_o[7];
	a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip6_o[6];
	a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip6_o[7];
	a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip7_o[6];
	a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip7_o[7];
	a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip8_o[6];
	a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip8_o[7];
	a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip9_o[6];
	a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip9_o[7];
	a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip10_o[6];
	a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip10_o[7];
	a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip11_o[6];
	a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip11_o[7];
	a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip12_o[6];
	a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip12_o[7];
	a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip13_o[6];
	a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip13_o[7];
	a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip14_o[6];
	a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip14_o[7];
	a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip15_o[6];
	a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip15_o[7];
// synthesis translate_off
	dummy_d_7 = dummy_s;
// synthesis translate_on
end
assign a7ddrphy_bitslip1_i = a7ddrphy_dq_i_data1;
assign a7ddrphy_bitslip2_i = a7ddrphy_dq_i_data2;
assign a7ddrphy_bitslip3_i = a7ddrphy_dq_i_data3;
assign a7ddrphy_bitslip4_i = a7ddrphy_dq_i_data4;
assign a7ddrphy_bitslip5_i = a7ddrphy_dq_i_data5;
assign a7ddrphy_bitslip6_i = a7ddrphy_dq_i_data6;
assign a7ddrphy_bitslip7_i = a7ddrphy_dq_i_data7;
assign a7ddrphy_bitslip8_i = a7ddrphy_dq_i_data8;
assign a7ddrphy_bitslip9_i = a7ddrphy_dq_i_data9;
assign a7ddrphy_bitslip10_i = a7ddrphy_dq_i_data10;
assign a7ddrphy_bitslip11_i = a7ddrphy_dq_i_data11;
assign a7ddrphy_bitslip12_i = a7ddrphy_dq_i_data12;
assign a7ddrphy_bitslip13_i = a7ddrphy_dq_i_data13;
assign a7ddrphy_bitslip14_i = a7ddrphy_dq_i_data14;
assign a7ddrphy_bitslip15_i = a7ddrphy_dq_i_data15;
assign a7ddrphy_rddata_en = {a7ddrphy_rddata_en_last, a7ddrphy_dfi_p2_rddata_en};
assign a7ddrphy_wrdata_en = {a7ddrphy_wrdata_en_last, a7ddrphy_dfi_p3_wrdata_en};
assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en[2];

// synthesis translate_off
reg dummy_d_8;
// synthesis translate_on
always @(*) begin
	a7ddrphy_dqs_oe <= 1'd0;
	if (a7ddrphy_wlevel_en_storage) begin
		a7ddrphy_dqs_oe <= 1'd1;
	end else begin
		a7ddrphy_dqs_oe <= a7ddrphy_dq_oe;
	end
// synthesis translate_off
	dummy_d_8 = dummy_s;
// synthesis translate_on
end
assign a7ddrphy_dqspattern0 = (a7ddrphy_wrdata_en[1] & (~a7ddrphy_wrdata_en[2]));
assign a7ddrphy_dqspattern1 = (a7ddrphy_wrdata_en[3] & (~a7ddrphy_wrdata_en[2]));

// synthesis translate_off
reg dummy_d_9;
// synthesis translate_on
always @(*) begin
	a7ddrphy_dqspattern_o0 <= 8'd0;
	a7ddrphy_dqspattern_o0 <= 7'd85;
	if (a7ddrphy_dqspattern0) begin
		a7ddrphy_dqspattern_o0 <= 5'd21;
	end
	if (a7ddrphy_dqspattern1) begin
		a7ddrphy_dqspattern_o0 <= 7'd84;
	end
	if (a7ddrphy_wlevel_en_storage) begin
		a7ddrphy_dqspattern_o0 <= 1'd0;
		if (a7ddrphy_wlevel_strobe_re) begin
			a7ddrphy_dqspattern_o0 <= 1'd1;
		end
	end
// synthesis translate_off
	dummy_d_9 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_10;
// synthesis translate_on
always @(*) begin
	a7ddrphy_bitslip0_o <= 8'd0;
	case (a7ddrphy_bitslip0_value)
		1'd0: begin
			a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[7:0];
		end
		1'd1: begin
			a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[8:1];
		end
		2'd2: begin
			a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[9:2];
		end
		2'd3: begin
			a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[10:3];
		end
		3'd4: begin
			a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[11:4];
		end
		3'd5: begin
			a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[12:5];
		end
		3'd6: begin
			a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[13:6];
		end
		3'd7: begin
			a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[14:7];
		end
		4'd8: begin
			a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[15:8];
		end
		4'd9: begin
			a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[16:9];
		end
		4'd10: begin
			a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[17:10];
		end
		4'd11: begin
			a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[18:11];
		end
		4'd12: begin
			a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[19:12];
		end
		4'd13: begin
			a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[20:13];
		end
		4'd14: begin
			a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[21:14];
		end
		4'd15: begin
			a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[22:15];
		end
	endcase
// synthesis translate_off
	dummy_d_10 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_11;
// synthesis translate_on
always @(*) begin
	a7ddrphy_bitslip1_o <= 8'd0;
	case (a7ddrphy_bitslip1_value)
		1'd0: begin
			a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[7:0];
		end
		1'd1: begin
			a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[8:1];
		end
		2'd2: begin
			a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[9:2];
		end
		2'd3: begin
			a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[10:3];
		end
		3'd4: begin
			a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[11:4];
		end
		3'd5: begin
			a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[12:5];
		end
		3'd6: begin
			a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[13:6];
		end
		3'd7: begin
			a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[14:7];
		end
		4'd8: begin
			a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[15:8];
		end
		4'd9: begin
			a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[16:9];
		end
		4'd10: begin
			a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[17:10];
		end
		4'd11: begin
			a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[18:11];
		end
		4'd12: begin
			a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[19:12];
		end
		4'd13: begin
			a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[20:13];
		end
		4'd14: begin
			a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[21:14];
		end
		4'd15: begin
			a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[22:15];
		end
	endcase
// synthesis translate_off
	dummy_d_11 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_12;
// synthesis translate_on
always @(*) begin
	a7ddrphy_bitslip2_o <= 8'd0;
	case (a7ddrphy_bitslip2_value)
		1'd0: begin
			a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[7:0];
		end
		1'd1: begin
			a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[8:1];
		end
		2'd2: begin
			a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[9:2];
		end
		2'd3: begin
			a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[10:3];
		end
		3'd4: begin
			a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[11:4];
		end
		3'd5: begin
			a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[12:5];
		end
		3'd6: begin
			a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[13:6];
		end
		3'd7: begin
			a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[14:7];
		end
		4'd8: begin
			a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[15:8];
		end
		4'd9: begin
			a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[16:9];
		end
		4'd10: begin
			a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[17:10];
		end
		4'd11: begin
			a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[18:11];
		end
		4'd12: begin
			a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[19:12];
		end
		4'd13: begin
			a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[20:13];
		end
		4'd14: begin
			a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[21:14];
		end
		4'd15: begin
			a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[22:15];
		end
	endcase
// synthesis translate_off
	dummy_d_12 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_13;
// synthesis translate_on
always @(*) begin
	a7ddrphy_bitslip3_o <= 8'd0;
	case (a7ddrphy_bitslip3_value)
		1'd0: begin
			a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[7:0];
		end
		1'd1: begin
			a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[8:1];
		end
		2'd2: begin
			a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[9:2];
		end
		2'd3: begin
			a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[10:3];
		end
		3'd4: begin
			a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[11:4];
		end
		3'd5: begin
			a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[12:5];
		end
		3'd6: begin
			a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[13:6];
		end
		3'd7: begin
			a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[14:7];
		end
		4'd8: begin
			a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[15:8];
		end
		4'd9: begin
			a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[16:9];
		end
		4'd10: begin
			a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[17:10];
		end
		4'd11: begin
			a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[18:11];
		end
		4'd12: begin
			a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[19:12];
		end
		4'd13: begin
			a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[20:13];
		end
		4'd14: begin
			a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[21:14];
		end
		4'd15: begin
			a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[22:15];
		end
	endcase
// synthesis translate_off
	dummy_d_13 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_14;
// synthesis translate_on
always @(*) begin
	a7ddrphy_bitslip4_o <= 8'd0;
	case (a7ddrphy_bitslip4_value)
		1'd0: begin
			a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[7:0];
		end
		1'd1: begin
			a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[8:1];
		end
		2'd2: begin
			a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[9:2];
		end
		2'd3: begin
			a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[10:3];
		end
		3'd4: begin
			a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[11:4];
		end
		3'd5: begin
			a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[12:5];
		end
		3'd6: begin
			a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[13:6];
		end
		3'd7: begin
			a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[14:7];
		end
		4'd8: begin
			a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[15:8];
		end
		4'd9: begin
			a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[16:9];
		end
		4'd10: begin
			a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[17:10];
		end
		4'd11: begin
			a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[18:11];
		end
		4'd12: begin
			a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[19:12];
		end
		4'd13: begin
			a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[20:13];
		end
		4'd14: begin
			a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[21:14];
		end
		4'd15: begin
			a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[22:15];
		end
	endcase
// synthesis translate_off
	dummy_d_14 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_15;
// synthesis translate_on
always @(*) begin
	a7ddrphy_bitslip5_o <= 8'd0;
	case (a7ddrphy_bitslip5_value)
		1'd0: begin
			a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[7:0];
		end
		1'd1: begin
			a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[8:1];
		end
		2'd2: begin
			a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[9:2];
		end
		2'd3: begin
			a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[10:3];
		end
		3'd4: begin
			a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[11:4];
		end
		3'd5: begin
			a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[12:5];
		end
		3'd6: begin
			a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[13:6];
		end
		3'd7: begin
			a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[14:7];
		end
		4'd8: begin
			a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[15:8];
		end
		4'd9: begin
			a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[16:9];
		end
		4'd10: begin
			a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[17:10];
		end
		4'd11: begin
			a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[18:11];
		end
		4'd12: begin
			a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[19:12];
		end
		4'd13: begin
			a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[20:13];
		end
		4'd14: begin
			a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[21:14];
		end
		4'd15: begin
			a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[22:15];
		end
	endcase
// synthesis translate_off
	dummy_d_15 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_16;
// synthesis translate_on
always @(*) begin
	a7ddrphy_bitslip6_o <= 8'd0;
	case (a7ddrphy_bitslip6_value)
		1'd0: begin
			a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[7:0];
		end
		1'd1: begin
			a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[8:1];
		end
		2'd2: begin
			a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[9:2];
		end
		2'd3: begin
			a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[10:3];
		end
		3'd4: begin
			a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[11:4];
		end
		3'd5: begin
			a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[12:5];
		end
		3'd6: begin
			a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[13:6];
		end
		3'd7: begin
			a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[14:7];
		end
		4'd8: begin
			a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[15:8];
		end
		4'd9: begin
			a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[16:9];
		end
		4'd10: begin
			a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[17:10];
		end
		4'd11: begin
			a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[18:11];
		end
		4'd12: begin
			a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[19:12];
		end
		4'd13: begin
			a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[20:13];
		end
		4'd14: begin
			a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[21:14];
		end
		4'd15: begin
			a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[22:15];
		end
	endcase
// synthesis translate_off
	dummy_d_16 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_17;
// synthesis translate_on
always @(*) begin
	a7ddrphy_bitslip7_o <= 8'd0;
	case (a7ddrphy_bitslip7_value)
		1'd0: begin
			a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[7:0];
		end
		1'd1: begin
			a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[8:1];
		end
		2'd2: begin
			a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[9:2];
		end
		2'd3: begin
			a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[10:3];
		end
		3'd4: begin
			a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[11:4];
		end
		3'd5: begin
			a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[12:5];
		end
		3'd6: begin
			a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[13:6];
		end
		3'd7: begin
			a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[14:7];
		end
		4'd8: begin
			a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[15:8];
		end
		4'd9: begin
			a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[16:9];
		end
		4'd10: begin
			a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[17:10];
		end
		4'd11: begin
			a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[18:11];
		end
		4'd12: begin
			a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[19:12];
		end
		4'd13: begin
			a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[20:13];
		end
		4'd14: begin
			a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[21:14];
		end
		4'd15: begin
			a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[22:15];
		end
	endcase
// synthesis translate_off
	dummy_d_17 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_18;
// synthesis translate_on
always @(*) begin
	a7ddrphy_bitslip8_o <= 8'd0;
	case (a7ddrphy_bitslip8_value)
		1'd0: begin
			a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[7:0];
		end
		1'd1: begin
			a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[8:1];
		end
		2'd2: begin
			a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[9:2];
		end
		2'd3: begin
			a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[10:3];
		end
		3'd4: begin
			a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[11:4];
		end
		3'd5: begin
			a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[12:5];
		end
		3'd6: begin
			a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[13:6];
		end
		3'd7: begin
			a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[14:7];
		end
		4'd8: begin
			a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[15:8];
		end
		4'd9: begin
			a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[16:9];
		end
		4'd10: begin
			a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[17:10];
		end
		4'd11: begin
			a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[18:11];
		end
		4'd12: begin
			a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[19:12];
		end
		4'd13: begin
			a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[20:13];
		end
		4'd14: begin
			a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[21:14];
		end
		4'd15: begin
			a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[22:15];
		end
	endcase
// synthesis translate_off
	dummy_d_18 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_19;
// synthesis translate_on
always @(*) begin
	a7ddrphy_bitslip9_o <= 8'd0;
	case (a7ddrphy_bitslip9_value)
		1'd0: begin
			a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[7:0];
		end
		1'd1: begin
			a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[8:1];
		end
		2'd2: begin
			a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[9:2];
		end
		2'd3: begin
			a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[10:3];
		end
		3'd4: begin
			a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[11:4];
		end
		3'd5: begin
			a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[12:5];
		end
		3'd6: begin
			a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[13:6];
		end
		3'd7: begin
			a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[14:7];
		end
		4'd8: begin
			a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[15:8];
		end
		4'd9: begin
			a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[16:9];
		end
		4'd10: begin
			a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[17:10];
		end
		4'd11: begin
			a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[18:11];
		end
		4'd12: begin
			a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[19:12];
		end
		4'd13: begin
			a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[20:13];
		end
		4'd14: begin
			a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[21:14];
		end
		4'd15: begin
			a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[22:15];
		end
	endcase
// synthesis translate_off
	dummy_d_19 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_20;
// synthesis translate_on
always @(*) begin
	a7ddrphy_bitslip10_o <= 8'd0;
	case (a7ddrphy_bitslip10_value)
		1'd0: begin
			a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[7:0];
		end
		1'd1: begin
			a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[8:1];
		end
		2'd2: begin
			a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[9:2];
		end
		2'd3: begin
			a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[10:3];
		end
		3'd4: begin
			a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[11:4];
		end
		3'd5: begin
			a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[12:5];
		end
		3'd6: begin
			a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[13:6];
		end
		3'd7: begin
			a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[14:7];
		end
		4'd8: begin
			a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[15:8];
		end
		4'd9: begin
			a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[16:9];
		end
		4'd10: begin
			a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[17:10];
		end
		4'd11: begin
			a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[18:11];
		end
		4'd12: begin
			a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[19:12];
		end
		4'd13: begin
			a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[20:13];
		end
		4'd14: begin
			a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[21:14];
		end
		4'd15: begin
			a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[22:15];
		end
	endcase
// synthesis translate_off
	dummy_d_20 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_21;
// synthesis translate_on
always @(*) begin
	a7ddrphy_bitslip11_o <= 8'd0;
	case (a7ddrphy_bitslip11_value)
		1'd0: begin
			a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[7:0];
		end
		1'd1: begin
			a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[8:1];
		end
		2'd2: begin
			a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[9:2];
		end
		2'd3: begin
			a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[10:3];
		end
		3'd4: begin
			a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[11:4];
		end
		3'd5: begin
			a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[12:5];
		end
		3'd6: begin
			a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[13:6];
		end
		3'd7: begin
			a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[14:7];
		end
		4'd8: begin
			a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[15:8];
		end
		4'd9: begin
			a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[16:9];
		end
		4'd10: begin
			a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[17:10];
		end
		4'd11: begin
			a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[18:11];
		end
		4'd12: begin
			a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[19:12];
		end
		4'd13: begin
			a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[20:13];
		end
		4'd14: begin
			a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[21:14];
		end
		4'd15: begin
			a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[22:15];
		end
	endcase
// synthesis translate_off
	dummy_d_21 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_22;
// synthesis translate_on
always @(*) begin
	a7ddrphy_bitslip12_o <= 8'd0;
	case (a7ddrphy_bitslip12_value)
		1'd0: begin
			a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[7:0];
		end
		1'd1: begin
			a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[8:1];
		end
		2'd2: begin
			a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[9:2];
		end
		2'd3: begin
			a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[10:3];
		end
		3'd4: begin
			a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[11:4];
		end
		3'd5: begin
			a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[12:5];
		end
		3'd6: begin
			a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[13:6];
		end
		3'd7: begin
			a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[14:7];
		end
		4'd8: begin
			a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[15:8];
		end
		4'd9: begin
			a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[16:9];
		end
		4'd10: begin
			a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[17:10];
		end
		4'd11: begin
			a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[18:11];
		end
		4'd12: begin
			a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[19:12];
		end
		4'd13: begin
			a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[20:13];
		end
		4'd14: begin
			a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[21:14];
		end
		4'd15: begin
			a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[22:15];
		end
	endcase
// synthesis translate_off
	dummy_d_22 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_23;
// synthesis translate_on
always @(*) begin
	a7ddrphy_bitslip13_o <= 8'd0;
	case (a7ddrphy_bitslip13_value)
		1'd0: begin
			a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[7:0];
		end
		1'd1: begin
			a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[8:1];
		end
		2'd2: begin
			a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[9:2];
		end
		2'd3: begin
			a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[10:3];
		end
		3'd4: begin
			a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[11:4];
		end
		3'd5: begin
			a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[12:5];
		end
		3'd6: begin
			a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[13:6];
		end
		3'd7: begin
			a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[14:7];
		end
		4'd8: begin
			a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[15:8];
		end
		4'd9: begin
			a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[16:9];
		end
		4'd10: begin
			a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[17:10];
		end
		4'd11: begin
			a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[18:11];
		end
		4'd12: begin
			a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[19:12];
		end
		4'd13: begin
			a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[20:13];
		end
		4'd14: begin
			a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[21:14];
		end
		4'd15: begin
			a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[22:15];
		end
	endcase
// synthesis translate_off
	dummy_d_23 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_24;
// synthesis translate_on
always @(*) begin
	a7ddrphy_bitslip14_o <= 8'd0;
	case (a7ddrphy_bitslip14_value)
		1'd0: begin
			a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[7:0];
		end
		1'd1: begin
			a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[8:1];
		end
		2'd2: begin
			a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[9:2];
		end
		2'd3: begin
			a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[10:3];
		end
		3'd4: begin
			a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[11:4];
		end
		3'd5: begin
			a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[12:5];
		end
		3'd6: begin
			a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[13:6];
		end
		3'd7: begin
			a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[14:7];
		end
		4'd8: begin
			a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[15:8];
		end
		4'd9: begin
			a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[16:9];
		end
		4'd10: begin
			a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[17:10];
		end
		4'd11: begin
			a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[18:11];
		end
		4'd12: begin
			a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[19:12];
		end
		4'd13: begin
			a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[20:13];
		end
		4'd14: begin
			a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[21:14];
		end
		4'd15: begin
			a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[22:15];
		end
	endcase
// synthesis translate_off
	dummy_d_24 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_25;
// synthesis translate_on
always @(*) begin
	a7ddrphy_bitslip15_o <= 8'd0;
	case (a7ddrphy_bitslip15_value)
		1'd0: begin
			a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[7:0];
		end
		1'd1: begin
			a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[8:1];
		end
		2'd2: begin
			a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[9:2];
		end
		2'd3: begin
			a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[10:3];
		end
		3'd4: begin
			a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[11:4];
		end
		3'd5: begin
			a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[12:5];
		end
		3'd6: begin
			a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[13:6];
		end
		3'd7: begin
			a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[14:7];
		end
		4'd8: begin
			a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[15:8];
		end
		4'd9: begin
			a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[16:9];
		end
		4'd10: begin
			a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[17:10];
		end
		4'd11: begin
			a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[18:11];
		end
		4'd12: begin
			a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[19:12];
		end
		4'd13: begin
			a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[20:13];
		end
		4'd14: begin
			a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[21:14];
		end
		4'd15: begin
			a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[22:15];
		end
	endcase
// synthesis translate_off
	dummy_d_25 = dummy_s;
// synthesis translate_on
end
assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address;
assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank;
assign a7ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n;
assign a7ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n;
assign a7ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n;
assign a7ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n;
assign a7ddrphy_dfi_p0_cke = litedramcore_master_p0_cke;
assign a7ddrphy_dfi_p0_odt = litedramcore_master_p0_odt;
assign a7ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n;
assign a7ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n;
assign a7ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata;
assign a7ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en;
assign a7ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask;
assign a7ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en;
assign litedramcore_master_p0_rddata = a7ddrphy_dfi_p0_rddata;
assign litedramcore_master_p0_rddata_valid = a7ddrphy_dfi_p0_rddata_valid;
assign a7ddrphy_dfi_p1_address = litedramcore_master_p1_address;
assign a7ddrphy_dfi_p1_bank = litedramcore_master_p1_bank;
assign a7ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n;
assign a7ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n;
assign a7ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n;
assign a7ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n;
assign a7ddrphy_dfi_p1_cke = litedramcore_master_p1_cke;
assign a7ddrphy_dfi_p1_odt = litedramcore_master_p1_odt;
assign a7ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n;
assign a7ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n;
assign a7ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata;
assign a7ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en;
assign a7ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask;
assign a7ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en;
assign litedramcore_master_p1_rddata = a7ddrphy_dfi_p1_rddata;
assign litedramcore_master_p1_rddata_valid = a7ddrphy_dfi_p1_rddata_valid;
assign a7ddrphy_dfi_p2_address = litedramcore_master_p2_address;
assign a7ddrphy_dfi_p2_bank = litedramcore_master_p2_bank;
assign a7ddrphy_dfi_p2_cas_n = litedramcore_master_p2_cas_n;
assign a7ddrphy_dfi_p2_cs_n = litedramcore_master_p2_cs_n;
assign a7ddrphy_dfi_p2_ras_n = litedramcore_master_p2_ras_n;
assign a7ddrphy_dfi_p2_we_n = litedramcore_master_p2_we_n;
assign a7ddrphy_dfi_p2_cke = litedramcore_master_p2_cke;
assign a7ddrphy_dfi_p2_odt = litedramcore_master_p2_odt;
assign a7ddrphy_dfi_p2_reset_n = litedramcore_master_p2_reset_n;
assign a7ddrphy_dfi_p2_act_n = litedramcore_master_p2_act_n;
assign a7ddrphy_dfi_p2_wrdata = litedramcore_master_p2_wrdata;
assign a7ddrphy_dfi_p2_wrdata_en = litedramcore_master_p2_wrdata_en;
assign a7ddrphy_dfi_p2_wrdata_mask = litedramcore_master_p2_wrdata_mask;
assign a7ddrphy_dfi_p2_rddata_en = litedramcore_master_p2_rddata_en;
assign litedramcore_master_p2_rddata = a7ddrphy_dfi_p2_rddata;
assign litedramcore_master_p2_rddata_valid = a7ddrphy_dfi_p2_rddata_valid;
assign a7ddrphy_dfi_p3_address = litedramcore_master_p3_address;
assign a7ddrphy_dfi_p3_bank = litedramcore_master_p3_bank;
assign a7ddrphy_dfi_p3_cas_n = litedramcore_master_p3_cas_n;
assign a7ddrphy_dfi_p3_cs_n = litedramcore_master_p3_cs_n;
assign a7ddrphy_dfi_p3_ras_n = litedramcore_master_p3_ras_n;
assign a7ddrphy_dfi_p3_we_n = litedramcore_master_p3_we_n;
assign a7ddrphy_dfi_p3_cke = litedramcore_master_p3_cke;
assign a7ddrphy_dfi_p3_odt = litedramcore_master_p3_odt;
assign a7ddrphy_dfi_p3_reset_n = litedramcore_master_p3_reset_n;
assign a7ddrphy_dfi_p3_act_n = litedramcore_master_p3_act_n;
assign a7ddrphy_dfi_p3_wrdata = litedramcore_master_p3_wrdata;
assign a7ddrphy_dfi_p3_wrdata_en = litedramcore_master_p3_wrdata_en;
assign a7ddrphy_dfi_p3_wrdata_mask = litedramcore_master_p3_wrdata_mask;
assign a7ddrphy_dfi_p3_rddata_en = litedramcore_master_p3_rddata_en;
assign litedramcore_master_p3_rddata = a7ddrphy_dfi_p3_rddata;
assign litedramcore_master_p3_rddata_valid = a7ddrphy_dfi_p3_rddata_valid;
assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address;
assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank;
assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n;
assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n;
assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n;
assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n;
assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke;
assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt;
assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n;
assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n;
assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata;
assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en;
assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask;
assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en;
assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata;
assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid;
assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address;
assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank;
assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n;
assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n;
assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n;
assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n;
assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke;
assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt;
assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n;
assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n;
assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata;
assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en;
assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask;
assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en;
assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata;
assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid;
assign litedramcore_slave_p2_address = litedramcore_dfi_p2_address;
assign litedramcore_slave_p2_bank = litedramcore_dfi_p2_bank;
assign litedramcore_slave_p2_cas_n = litedramcore_dfi_p2_cas_n;
assign litedramcore_slave_p2_cs_n = litedramcore_dfi_p2_cs_n;
assign litedramcore_slave_p2_ras_n = litedramcore_dfi_p2_ras_n;
assign litedramcore_slave_p2_we_n = litedramcore_dfi_p2_we_n;
assign litedramcore_slave_p2_cke = litedramcore_dfi_p2_cke;
assign litedramcore_slave_p2_odt = litedramcore_dfi_p2_odt;
assign litedramcore_slave_p2_reset_n = litedramcore_dfi_p2_reset_n;
assign litedramcore_slave_p2_act_n = litedramcore_dfi_p2_act_n;
assign litedramcore_slave_p2_wrdata = litedramcore_dfi_p2_wrdata;
assign litedramcore_slave_p2_wrdata_en = litedramcore_dfi_p2_wrdata_en;
assign litedramcore_slave_p2_wrdata_mask = litedramcore_dfi_p2_wrdata_mask;
assign litedramcore_slave_p2_rddata_en = litedramcore_dfi_p2_rddata_en;
assign litedramcore_dfi_p2_rddata = litedramcore_slave_p2_rddata;
assign litedramcore_dfi_p2_rddata_valid = litedramcore_slave_p2_rddata_valid;
assign litedramcore_slave_p3_address = litedramcore_dfi_p3_address;
assign litedramcore_slave_p3_bank = litedramcore_dfi_p3_bank;
assign litedramcore_slave_p3_cas_n = litedramcore_dfi_p3_cas_n;
assign litedramcore_slave_p3_cs_n = litedramcore_dfi_p3_cs_n;
assign litedramcore_slave_p3_ras_n = litedramcore_dfi_p3_ras_n;
assign litedramcore_slave_p3_we_n = litedramcore_dfi_p3_we_n;
assign litedramcore_slave_p3_cke = litedramcore_dfi_p3_cke;
assign litedramcore_slave_p3_odt = litedramcore_dfi_p3_odt;
assign litedramcore_slave_p3_reset_n = litedramcore_dfi_p3_reset_n;
assign litedramcore_slave_p3_act_n = litedramcore_dfi_p3_act_n;
assign litedramcore_slave_p3_wrdata = litedramcore_dfi_p3_wrdata;
assign litedramcore_slave_p3_wrdata_en = litedramcore_dfi_p3_wrdata_en;
assign litedramcore_slave_p3_wrdata_mask = litedramcore_dfi_p3_wrdata_mask;
assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en;
assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata;
assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid;

// synthesis translate_off
reg dummy_d_26;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p1_wrdata_en <= 1'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
	end else begin
		litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en;
	end
// synthesis translate_off
	dummy_d_26 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_27;
// synthesis translate_on
always @(*) begin
	litedramcore_inti_p2_rddata_valid <= 1'd0;
	if (litedramcore_storage[0]) begin
	end else begin
		litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
	end
// synthesis translate_off
	dummy_d_27 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_28;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p1_wrdata_mask <= 4'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
	end else begin
		litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask;
	end
// synthesis translate_off
	dummy_d_28 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_29;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p1_rddata_en <= 1'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
	end else begin
		litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en;
	end
// synthesis translate_off
	dummy_d_29 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_30;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p2_address <= 15'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p2_address <= litedramcore_slave_p2_address;
	end else begin
		litedramcore_master_p2_address <= litedramcore_inti_p2_address;
	end
// synthesis translate_off
	dummy_d_30 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_31;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p2_bank <= 3'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
	end else begin
		litedramcore_master_p2_bank <= litedramcore_inti_p2_bank;
	end
// synthesis translate_off
	dummy_d_31 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_32;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p2_cas_n <= 1'd1;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
	end else begin
		litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n;
	end
// synthesis translate_off
	dummy_d_32 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_33;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p2_cs_n <= 1'd1;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
	end else begin
		litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n;
	end
// synthesis translate_off
	dummy_d_33 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_34;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p2_ras_n <= 1'd1;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
	end else begin
		litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n;
	end
// synthesis translate_off
	dummy_d_34 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_35;
// synthesis translate_on
always @(*) begin
	litedramcore_slave_p2_rddata <= 32'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
	end else begin
	end
// synthesis translate_off
	dummy_d_35 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_36;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p2_we_n <= 1'd1;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
	end else begin
		litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n;
	end
// synthesis translate_off
	dummy_d_36 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_37;
// synthesis translate_on
always @(*) begin
	litedramcore_slave_p2_rddata_valid <= 1'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
	end else begin
	end
// synthesis translate_off
	dummy_d_37 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_38;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p2_cke <= 1'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
	end else begin
		litedramcore_master_p2_cke <= litedramcore_inti_p2_cke;
	end
// synthesis translate_off
	dummy_d_38 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_39;
// synthesis translate_on
always @(*) begin
	litedramcore_inti_p2_rddata <= 32'd0;
	if (litedramcore_storage[0]) begin
	end else begin
		litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata;
	end
// synthesis translate_off
	dummy_d_39 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_40;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p2_odt <= 1'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
	end else begin
		litedramcore_master_p2_odt <= litedramcore_inti_p2_odt;
	end
// synthesis translate_off
	dummy_d_40 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_41;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p2_reset_n <= 1'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
	end else begin
		litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n;
	end
// synthesis translate_off
	dummy_d_41 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_42;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p2_act_n <= 1'd1;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
	end else begin
		litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n;
	end
// synthesis translate_off
	dummy_d_42 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_43;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p2_wrdata <= 32'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
	end else begin
		litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata;
	end
// synthesis translate_off
	dummy_d_43 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_44;
// synthesis translate_on
always @(*) begin
	litedramcore_inti_p3_rddata <= 32'd0;
	if (litedramcore_storage[0]) begin
	end else begin
		litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata;
	end
// synthesis translate_off
	dummy_d_44 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_45;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p2_wrdata_en <= 1'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
	end else begin
		litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en;
	end
// synthesis translate_off
	dummy_d_45 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_46;
// synthesis translate_on
always @(*) begin
	litedramcore_inti_p3_rddata_valid <= 1'd0;
	if (litedramcore_storage[0]) begin
	end else begin
		litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
	end
// synthesis translate_off
	dummy_d_46 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_47;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p2_wrdata_mask <= 4'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
	end else begin
		litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask;
	end
// synthesis translate_off
	dummy_d_47 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_48;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p2_rddata_en <= 1'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
	end else begin
		litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en;
	end
// synthesis translate_off
	dummy_d_48 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_49;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p3_address <= 15'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p3_address <= litedramcore_slave_p3_address;
	end else begin
		litedramcore_master_p3_address <= litedramcore_inti_p3_address;
	end
// synthesis translate_off
	dummy_d_49 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_50;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p3_bank <= 3'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
	end else begin
		litedramcore_master_p3_bank <= litedramcore_inti_p3_bank;
	end
// synthesis translate_off
	dummy_d_50 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_51;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p3_cas_n <= 1'd1;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
	end else begin
		litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n;
	end
// synthesis translate_off
	dummy_d_51 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_52;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p3_cs_n <= 1'd1;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
	end else begin
		litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n;
	end
// synthesis translate_off
	dummy_d_52 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_53;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p3_ras_n <= 1'd1;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
	end else begin
		litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n;
	end
// synthesis translate_off
	dummy_d_53 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_54;
// synthesis translate_on
always @(*) begin
	litedramcore_slave_p3_rddata <= 32'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
	end else begin
	end
// synthesis translate_off
	dummy_d_54 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_55;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p3_we_n <= 1'd1;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
	end else begin
		litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n;
	end
// synthesis translate_off
	dummy_d_55 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_56;
// synthesis translate_on
always @(*) begin
	litedramcore_slave_p3_rddata_valid <= 1'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
	end else begin
	end
// synthesis translate_off
	dummy_d_56 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_57;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p3_cke <= 1'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
	end else begin
		litedramcore_master_p3_cke <= litedramcore_inti_p3_cke;
	end
// synthesis translate_off
	dummy_d_57 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_58;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p3_odt <= 1'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
	end else begin
		litedramcore_master_p3_odt <= litedramcore_inti_p3_odt;
	end
// synthesis translate_off
	dummy_d_58 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_59;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p3_reset_n <= 1'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
	end else begin
		litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n;
	end
// synthesis translate_off
	dummy_d_59 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_60;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p3_act_n <= 1'd1;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
	end else begin
		litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n;
	end
// synthesis translate_off
	dummy_d_60 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_61;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p3_wrdata <= 32'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
	end else begin
		litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata;
	end
// synthesis translate_off
	dummy_d_61 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_62;
// synthesis translate_on
always @(*) begin
	litedramcore_inti_p0_rddata <= 32'd0;
	if (litedramcore_storage[0]) begin
	end else begin
		litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata;
	end
// synthesis translate_off
	dummy_d_62 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_63;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p3_wrdata_en <= 1'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
	end else begin
		litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en;
	end
// synthesis translate_off
	dummy_d_63 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_64;
// synthesis translate_on
always @(*) begin
	litedramcore_inti_p0_rddata_valid <= 1'd0;
	if (litedramcore_storage[0]) begin
	end else begin
		litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
	end
// synthesis translate_off
	dummy_d_64 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_65;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p3_wrdata_mask <= 4'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
	end else begin
		litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask;
	end
// synthesis translate_off
	dummy_d_65 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_66;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p3_rddata_en <= 1'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
	end else begin
		litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en;
	end
// synthesis translate_off
	dummy_d_66 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_67;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p0_address <= 15'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p0_address <= litedramcore_slave_p0_address;
	end else begin
		litedramcore_master_p0_address <= litedramcore_inti_p0_address;
	end
// synthesis translate_off
	dummy_d_67 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_68;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p0_bank <= 3'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
	end else begin
		litedramcore_master_p0_bank <= litedramcore_inti_p0_bank;
	end
// synthesis translate_off
	dummy_d_68 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_69;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p0_cas_n <= 1'd1;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
	end else begin
		litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n;
	end
// synthesis translate_off
	dummy_d_69 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_70;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p0_cs_n <= 1'd1;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
	end else begin
		litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n;
	end
// synthesis translate_off
	dummy_d_70 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_71;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p0_ras_n <= 1'd1;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
	end else begin
		litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n;
	end
// synthesis translate_off
	dummy_d_71 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_72;
// synthesis translate_on
always @(*) begin
	litedramcore_slave_p0_rddata <= 32'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
	end else begin
	end
// synthesis translate_off
	dummy_d_72 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_73;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p0_we_n <= 1'd1;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
	end else begin
		litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n;
	end
// synthesis translate_off
	dummy_d_73 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_74;
// synthesis translate_on
always @(*) begin
	litedramcore_slave_p0_rddata_valid <= 1'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
	end else begin
	end
// synthesis translate_off
	dummy_d_74 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_75;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p0_cke <= 1'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
	end else begin
		litedramcore_master_p0_cke <= litedramcore_inti_p0_cke;
	end
// synthesis translate_off
	dummy_d_75 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_76;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p0_odt <= 1'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
	end else begin
		litedramcore_master_p0_odt <= litedramcore_inti_p0_odt;
	end
// synthesis translate_off
	dummy_d_76 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_77;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p0_reset_n <= 1'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
	end else begin
		litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n;
	end
// synthesis translate_off
	dummy_d_77 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_78;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p0_act_n <= 1'd1;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
	end else begin
		litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n;
	end
// synthesis translate_off
	dummy_d_78 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_79;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p0_wrdata <= 32'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
	end else begin
		litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata;
	end
// synthesis translate_off
	dummy_d_79 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_80;
// synthesis translate_on
always @(*) begin
	litedramcore_inti_p1_rddata <= 32'd0;
	if (litedramcore_storage[0]) begin
	end else begin
		litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata;
	end
// synthesis translate_off
	dummy_d_80 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_81;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p0_wrdata_en <= 1'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
	end else begin
		litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en;
	end
// synthesis translate_off
	dummy_d_81 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_82;
// synthesis translate_on
always @(*) begin
	litedramcore_inti_p1_rddata_valid <= 1'd0;
	if (litedramcore_storage[0]) begin
	end else begin
		litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
	end
// synthesis translate_off
	dummy_d_82 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_83;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p0_wrdata_mask <= 4'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
	end else begin
		litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask;
	end
// synthesis translate_off
	dummy_d_83 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_84;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p0_rddata_en <= 1'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
	end else begin
		litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en;
	end
// synthesis translate_off
	dummy_d_84 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_85;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p1_address <= 15'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p1_address <= litedramcore_slave_p1_address;
	end else begin
		litedramcore_master_p1_address <= litedramcore_inti_p1_address;
	end
// synthesis translate_off
	dummy_d_85 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_86;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p1_bank <= 3'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
	end else begin
		litedramcore_master_p1_bank <= litedramcore_inti_p1_bank;
	end
// synthesis translate_off
	dummy_d_86 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_87;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p1_cas_n <= 1'd1;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
	end else begin
		litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n;
	end
// synthesis translate_off
	dummy_d_87 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_88;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p1_cs_n <= 1'd1;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
	end else begin
		litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n;
	end
// synthesis translate_off
	dummy_d_88 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_89;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p1_ras_n <= 1'd1;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
	end else begin
		litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n;
	end
// synthesis translate_off
	dummy_d_89 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_90;
// synthesis translate_on
always @(*) begin
	litedramcore_slave_p1_rddata <= 32'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
	end else begin
	end
// synthesis translate_off
	dummy_d_90 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_91;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p1_we_n <= 1'd1;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
	end else begin
		litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n;
	end
// synthesis translate_off
	dummy_d_91 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_92;
// synthesis translate_on
always @(*) begin
	litedramcore_slave_p1_rddata_valid <= 1'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
	end else begin
	end
// synthesis translate_off
	dummy_d_92 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_93;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p1_cke <= 1'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
	end else begin
		litedramcore_master_p1_cke <= litedramcore_inti_p1_cke;
	end
// synthesis translate_off
	dummy_d_93 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_94;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p1_odt <= 1'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
	end else begin
		litedramcore_master_p1_odt <= litedramcore_inti_p1_odt;
	end
// synthesis translate_off
	dummy_d_94 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_95;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p1_reset_n <= 1'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
	end else begin
		litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n;
	end
// synthesis translate_off
	dummy_d_95 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_96;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p1_act_n <= 1'd1;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
	end else begin
		litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n;
	end
// synthesis translate_off
	dummy_d_96 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_97;
// synthesis translate_on
always @(*) begin
	litedramcore_master_p1_wrdata <= 32'd0;
	if (litedramcore_storage[0]) begin
		litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
	end else begin
		litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata;
	end
// synthesis translate_off
	dummy_d_97 = dummy_s;
// synthesis translate_on
end
assign litedramcore_inti_p0_cke = litedramcore_storage[1];
assign litedramcore_inti_p1_cke = litedramcore_storage[1];
assign litedramcore_inti_p2_cke = litedramcore_storage[1];
assign litedramcore_inti_p3_cke = litedramcore_storage[1];
assign litedramcore_inti_p0_odt = litedramcore_storage[2];
assign litedramcore_inti_p1_odt = litedramcore_storage[2];
assign litedramcore_inti_p2_odt = litedramcore_storage[2];
assign litedramcore_inti_p3_odt = litedramcore_storage[2];
assign litedramcore_inti_p0_reset_n = litedramcore_storage[3];
assign litedramcore_inti_p1_reset_n = litedramcore_storage[3];
assign litedramcore_inti_p2_reset_n = litedramcore_storage[3];
assign litedramcore_inti_p3_reset_n = litedramcore_storage[3];

// synthesis translate_off
reg dummy_d_98;
// synthesis translate_on
always @(*) begin
	litedramcore_inti_p0_cs_n <= 1'd1;
	if (litedramcore_phaseinjector0_command_issue_re) begin
		litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}};
	end else begin
		litedramcore_inti_p0_cs_n <= {1{1'd1}};
	end
// synthesis translate_off
	dummy_d_98 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_99;
// synthesis translate_on
always @(*) begin
	litedramcore_inti_p0_ras_n <= 1'd1;
	if (litedramcore_phaseinjector0_command_issue_re) begin
		litedramcore_inti_p0_ras_n <= (~litedramcore_phaseinjector0_command_storage[3]);
	end else begin
		litedramcore_inti_p0_ras_n <= 1'd1;
	end
// synthesis translate_off
	dummy_d_99 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_100;
// synthesis translate_on
always @(*) begin
	litedramcore_inti_p0_we_n <= 1'd1;
	if (litedramcore_phaseinjector0_command_issue_re) begin
		litedramcore_inti_p0_we_n <= (~litedramcore_phaseinjector0_command_storage[1]);
	end else begin
		litedramcore_inti_p0_we_n <= 1'd1;
	end
// synthesis translate_off
	dummy_d_100 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_101;
// synthesis translate_on
always @(*) begin
	litedramcore_inti_p0_cas_n <= 1'd1;
	if (litedramcore_phaseinjector0_command_issue_re) begin
		litedramcore_inti_p0_cas_n <= (~litedramcore_phaseinjector0_command_storage[2]);
	end else begin
		litedramcore_inti_p0_cas_n <= 1'd1;
	end
// synthesis translate_off
	dummy_d_101 = dummy_s;
// synthesis translate_on
end
assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage;
assign litedramcore_inti_p0_bank = litedramcore_phaseinjector0_baddress_storage;
assign litedramcore_inti_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[4]);
assign litedramcore_inti_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[5]);
assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
assign litedramcore_inti_p0_wrdata_mask = 1'd0;

// synthesis translate_off
reg dummy_d_102;
// synthesis translate_on
always @(*) begin
	litedramcore_inti_p1_cs_n <= 1'd1;
	if (litedramcore_phaseinjector1_command_issue_re) begin
		litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}};
	end else begin
		litedramcore_inti_p1_cs_n <= {1{1'd1}};
	end
// synthesis translate_off
	dummy_d_102 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_103;
// synthesis translate_on
always @(*) begin
	litedramcore_inti_p1_ras_n <= 1'd1;
	if (litedramcore_phaseinjector1_command_issue_re) begin
		litedramcore_inti_p1_ras_n <= (~litedramcore_phaseinjector1_command_storage[3]);
	end else begin
		litedramcore_inti_p1_ras_n <= 1'd1;
	end
// synthesis translate_off
	dummy_d_103 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_104;
// synthesis translate_on
always @(*) begin
	litedramcore_inti_p1_we_n <= 1'd1;
	if (litedramcore_phaseinjector1_command_issue_re) begin
		litedramcore_inti_p1_we_n <= (~litedramcore_phaseinjector1_command_storage[1]);
	end else begin
		litedramcore_inti_p1_we_n <= 1'd1;
	end
// synthesis translate_off
	dummy_d_104 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_105;
// synthesis translate_on
always @(*) begin
	litedramcore_inti_p1_cas_n <= 1'd1;
	if (litedramcore_phaseinjector1_command_issue_re) begin
		litedramcore_inti_p1_cas_n <= (~litedramcore_phaseinjector1_command_storage[2]);
	end else begin
		litedramcore_inti_p1_cas_n <= 1'd1;
	end
// synthesis translate_off
	dummy_d_105 = dummy_s;
// synthesis translate_on
end
assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage;
assign litedramcore_inti_p1_bank = litedramcore_phaseinjector1_baddress_storage;
assign litedramcore_inti_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[4]);
assign litedramcore_inti_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[5]);
assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
assign litedramcore_inti_p1_wrdata_mask = 1'd0;

// synthesis translate_off
reg dummy_d_106;
// synthesis translate_on
always @(*) begin
	litedramcore_inti_p2_cs_n <= 1'd1;
	if (litedramcore_phaseinjector2_command_issue_re) begin
		litedramcore_inti_p2_cs_n <= {1{(~litedramcore_phaseinjector2_command_storage[0])}};
	end else begin
		litedramcore_inti_p2_cs_n <= {1{1'd1}};
	end
// synthesis translate_off
	dummy_d_106 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_107;
// synthesis translate_on
always @(*) begin
	litedramcore_inti_p2_ras_n <= 1'd1;
	if (litedramcore_phaseinjector2_command_issue_re) begin
		litedramcore_inti_p2_ras_n <= (~litedramcore_phaseinjector2_command_storage[3]);
	end else begin
		litedramcore_inti_p2_ras_n <= 1'd1;
	end
// synthesis translate_off
	dummy_d_107 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_108;
// synthesis translate_on
always @(*) begin
	litedramcore_inti_p2_we_n <= 1'd1;
	if (litedramcore_phaseinjector2_command_issue_re) begin
		litedramcore_inti_p2_we_n <= (~litedramcore_phaseinjector2_command_storage[1]);
	end else begin
		litedramcore_inti_p2_we_n <= 1'd1;
	end
// synthesis translate_off
	dummy_d_108 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_109;
// synthesis translate_on
always @(*) begin
	litedramcore_inti_p2_cas_n <= 1'd1;
	if (litedramcore_phaseinjector2_command_issue_re) begin
		litedramcore_inti_p2_cas_n <= (~litedramcore_phaseinjector2_command_storage[2]);
	end else begin
		litedramcore_inti_p2_cas_n <= 1'd1;
	end
// synthesis translate_off
	dummy_d_109 = dummy_s;
// synthesis translate_on
end
assign litedramcore_inti_p2_address = litedramcore_phaseinjector2_address_storage;
assign litedramcore_inti_p2_bank = litedramcore_phaseinjector2_baddress_storage;
assign litedramcore_inti_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[4]);
assign litedramcore_inti_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[5]);
assign litedramcore_inti_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage;
assign litedramcore_inti_p2_wrdata_mask = 1'd0;

// synthesis translate_off
reg dummy_d_110;
// synthesis translate_on
always @(*) begin
	litedramcore_inti_p3_cs_n <= 1'd1;
	if (litedramcore_phaseinjector3_command_issue_re) begin
		litedramcore_inti_p3_cs_n <= {1{(~litedramcore_phaseinjector3_command_storage[0])}};
	end else begin
		litedramcore_inti_p3_cs_n <= {1{1'd1}};
	end
// synthesis translate_off
	dummy_d_110 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_111;
// synthesis translate_on
always @(*) begin
	litedramcore_inti_p3_ras_n <= 1'd1;
	if (litedramcore_phaseinjector3_command_issue_re) begin
		litedramcore_inti_p3_ras_n <= (~litedramcore_phaseinjector3_command_storage[3]);
	end else begin
		litedramcore_inti_p3_ras_n <= 1'd1;
	end
// synthesis translate_off
	dummy_d_111 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_112;
// synthesis translate_on
always @(*) begin
	litedramcore_inti_p3_we_n <= 1'd1;
	if (litedramcore_phaseinjector3_command_issue_re) begin
		litedramcore_inti_p3_we_n <= (~litedramcore_phaseinjector3_command_storage[1]);
	end else begin
		litedramcore_inti_p3_we_n <= 1'd1;
	end
// synthesis translate_off
	dummy_d_112 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_113;
// synthesis translate_on
always @(*) begin
	litedramcore_inti_p3_cas_n <= 1'd1;
	if (litedramcore_phaseinjector3_command_issue_re) begin
		litedramcore_inti_p3_cas_n <= (~litedramcore_phaseinjector3_command_storage[2]);
	end else begin
		litedramcore_inti_p3_cas_n <= 1'd1;
	end
// synthesis translate_off
	dummy_d_113 = dummy_s;
// synthesis translate_on
end
assign litedramcore_inti_p3_address = litedramcore_phaseinjector3_address_storage;
assign litedramcore_inti_p3_bank = litedramcore_phaseinjector3_baddress_storage;
assign litedramcore_inti_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_command_storage[4]);
assign litedramcore_inti_p3_rddata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_command_storage[5]);
assign litedramcore_inti_p3_wrdata = litedramcore_phaseinjector3_wrdata_storage;
assign litedramcore_inti_p3_wrdata_mask = 1'd0;
assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid;
assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready;
assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we;
assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr;
assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock;
assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready;
assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid;
assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid;
assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready;
assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we;
assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr;
assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock;
assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready;
assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid;
assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid;
assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready;
assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we;
assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr;
assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock;
assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready;
assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid;
assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid;
assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready;
assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we;
assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr;
assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock;
assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready;
assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid;
assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid;
assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready;
assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we;
assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr;
assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock;
assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready;
assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid;
assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid;
assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready;
assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we;
assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr;
assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock;
assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready;
assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid;
assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid;
assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready;
assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we;
assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr;
assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock;
assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready;
assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid;
assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid;
assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready;
assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we;
assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr;
assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock;
assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready;
assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid;
assign litedramcore_timer_wait = (~litedramcore_timer_done0);
assign litedramcore_postponer_req_i = litedramcore_timer_done0;
assign litedramcore_wants_refresh = litedramcore_postponer_req_o;
assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0;
assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done);
assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0);
assign litedramcore_timer_done0 = litedramcore_timer_done1;
assign litedramcore_timer_count0 = litedramcore_timer_count1;
assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0));
assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0));
assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0);
assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1;
assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;

// synthesis translate_off
reg dummy_d_114;
// synthesis translate_on
always @(*) begin
	refresher_next_state <= 2'd0;
	refresher_next_state <= refresher_state;
	case (refresher_state)
		1'd1: begin
			if (litedramcore_cmd_ready) begin
				refresher_next_state <= 2'd2;
			end
		end
		2'd2: begin
			if (litedramcore_sequencer_done0) begin
				if (litedramcore_wants_zqcs) begin
					refresher_next_state <= 2'd3;
				end else begin
					refresher_next_state <= 1'd0;
				end
			end
		end
		2'd3: begin
			if (litedramcore_zqcs_executer_done) begin
				refresher_next_state <= 1'd0;
			end
		end
		default: begin
			if (1'd1) begin
				if (litedramcore_wants_refresh) begin
					refresher_next_state <= 1'd1;
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_114 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_115;
// synthesis translate_on
always @(*) begin
	litedramcore_sequencer_start0 <= 1'd0;
	case (refresher_state)
		1'd1: begin
			if (litedramcore_cmd_ready) begin
				litedramcore_sequencer_start0 <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_115 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_116;
// synthesis translate_on
always @(*) begin
	litedramcore_cmd_valid <= 1'd0;
	case (refresher_state)
		1'd1: begin
			litedramcore_cmd_valid <= 1'd1;
		end
		2'd2: begin
			litedramcore_cmd_valid <= 1'd1;
			if (litedramcore_sequencer_done0) begin
				if (litedramcore_wants_zqcs) begin
				end else begin
					litedramcore_cmd_valid <= 1'd0;
				end
			end
		end
		2'd3: begin
			litedramcore_cmd_valid <= 1'd1;
			if (litedramcore_zqcs_executer_done) begin
				litedramcore_cmd_valid <= 1'd0;
			end
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_116 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_117;
// synthesis translate_on
always @(*) begin
	litedramcore_zqcs_executer_start <= 1'd0;
	case (refresher_state)
		1'd1: begin
		end
		2'd2: begin
			if (litedramcore_sequencer_done0) begin
				if (litedramcore_wants_zqcs) begin
					litedramcore_zqcs_executer_start <= 1'd1;
				end else begin
				end
			end
		end
		2'd3: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_117 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_118;
// synthesis translate_on
always @(*) begin
	litedramcore_cmd_last <= 1'd0;
	case (refresher_state)
		1'd1: begin
		end
		2'd2: begin
			if (litedramcore_sequencer_done0) begin
				if (litedramcore_wants_zqcs) begin
				end else begin
					litedramcore_cmd_last <= 1'd1;
				end
			end
		end
		2'd3: begin
			if (litedramcore_zqcs_executer_done) begin
				litedramcore_cmd_last <= 1'd1;
			end
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_118 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid;
assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr;
assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready;
assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid);
assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]);
assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0;

// synthesis translate_off
reg dummy_d_119;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine0_cmd_payload_a <= 15'd0;
	if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
		litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7];
	end else begin
		litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
	end
// synthesis translate_off
	dummy_d_119 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write);
assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);

// synthesis translate_off
reg dummy_d_120;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine0_auto_precharge <= 1'd0;
	if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
		if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7])) begin
			litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
		end
	end
// synthesis translate_off
	dummy_d_120 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;

// synthesis translate_off
reg dummy_d_121;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
	if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
		litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
	end else begin
		litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
	end
// synthesis translate_off
	dummy_d_121 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready);

// synthesis translate_off
reg dummy_d_122;
// synthesis translate_on
always @(*) begin
	bankmachine0_next_state <= 4'd0;
	bankmachine0_next_state <= bankmachine0_state;
	case (bankmachine0_state)
		1'd1: begin
			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
				if (litedramcore_bankmachine0_cmd_ready) begin
					bankmachine0_next_state <= 3'd5;
				end
			end
		end
		2'd2: begin
			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
				bankmachine0_next_state <= 3'd5;
			end
		end
		2'd3: begin
			if (litedramcore_bankmachine0_trccon_ready) begin
				if (litedramcore_bankmachine0_cmd_ready) begin
					bankmachine0_next_state <= 3'd7;
				end
			end
		end
		3'd4: begin
			if ((~litedramcore_bankmachine0_refresh_req)) begin
				bankmachine0_next_state <= 1'd0;
			end
		end
		3'd5: begin
			bankmachine0_next_state <= 3'd6;
		end
		3'd6: begin
			bankmachine0_next_state <= 2'd3;
		end
		3'd7: begin
			bankmachine0_next_state <= 4'd8;
		end
		4'd8: begin
			bankmachine0_next_state <= 1'd0;
		end
		default: begin
			if (litedramcore_bankmachine0_refresh_req) begin
				bankmachine0_next_state <= 3'd4;
			end else begin
				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine0_row_opened) begin
						if (litedramcore_bankmachine0_row_hit) begin
							if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
								bankmachine0_next_state <= 2'd2;
							end
						end else begin
							bankmachine0_next_state <= 1'd1;
						end
					end else begin
						bankmachine0_next_state <= 2'd3;
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_122 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_123;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine0_row_open <= 1'd0;
	case (bankmachine0_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine0_trccon_ready) begin
				litedramcore_bankmachine0_row_open <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_123 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_124;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine0_row_close <= 1'd0;
	case (bankmachine0_state)
		1'd1: begin
			litedramcore_bankmachine0_row_close <= 1'd1;
		end
		2'd2: begin
			litedramcore_bankmachine0_row_close <= 1'd1;
		end
		2'd3: begin
		end
		3'd4: begin
			litedramcore_bankmachine0_row_close <= 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_124 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_125;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
	case (bankmachine0_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine0_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine0_row_opened) begin
						if (litedramcore_bankmachine0_row_hit) begin
							litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_125 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_126;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
	case (bankmachine0_state)
		1'd1: begin
			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
				litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine0_trccon_ready) begin
				litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_126 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_127;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
	case (bankmachine0_state)
		1'd1: begin
			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
				litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine0_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine0_row_opened) begin
						if (litedramcore_bankmachine0_row_hit) begin
							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_127 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_128;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
	case (bankmachine0_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine0_trccon_ready) begin
				litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_128 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_129;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
	case (bankmachine0_state)
		1'd1: begin
			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
				litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine0_trccon_ready) begin
				litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
			end
		end
		3'd4: begin
			litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_129 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_130;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
	case (bankmachine0_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine0_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine0_row_opened) begin
						if (litedramcore_bankmachine0_row_hit) begin
							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_130 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_131;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
	case (bankmachine0_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine0_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine0_row_opened) begin
						if (litedramcore_bankmachine0_row_hit) begin
							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_131 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_132;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
	case (bankmachine0_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine0_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine0_row_opened) begin
						if (litedramcore_bankmachine0_row_hit) begin
							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_132 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_133;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
	case (bankmachine0_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine0_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine0_row_opened) begin
						if (litedramcore_bankmachine0_row_hit) begin
							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_133 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_134;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine0_refresh_gnt <= 1'd0;
	case (bankmachine0_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
			if (litedramcore_bankmachine0_twtpcon_ready) begin
				litedramcore_bankmachine0_refresh_gnt <= 1'd1;
			end
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_134 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_135;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine0_cmd_valid <= 1'd0;
	case (bankmachine0_state)
		1'd1: begin
			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
				litedramcore_bankmachine0_cmd_valid <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine0_trccon_ready) begin
				litedramcore_bankmachine0_cmd_valid <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine0_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine0_row_opened) begin
						if (litedramcore_bankmachine0_row_hit) begin
							litedramcore_bankmachine0_cmd_valid <= 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_135 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid;
assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr;
assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready;
assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid);
assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]);
assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1;

// synthesis translate_off
reg dummy_d_136;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine1_cmd_payload_a <= 15'd0;
	if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
		litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7];
	end else begin
		litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
	end
// synthesis translate_off
	dummy_d_136 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write);
assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);

// synthesis translate_off
reg dummy_d_137;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine1_auto_precharge <= 1'd0;
	if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
		if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7])) begin
			litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
		end
	end
// synthesis translate_off
	dummy_d_137 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;

// synthesis translate_off
reg dummy_d_138;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
	if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
		litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
	end else begin
		litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
	end
// synthesis translate_off
	dummy_d_138 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready);

// synthesis translate_off
reg dummy_d_139;
// synthesis translate_on
always @(*) begin
	bankmachine1_next_state <= 4'd0;
	bankmachine1_next_state <= bankmachine1_state;
	case (bankmachine1_state)
		1'd1: begin
			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
				if (litedramcore_bankmachine1_cmd_ready) begin
					bankmachine1_next_state <= 3'd5;
				end
			end
		end
		2'd2: begin
			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
				bankmachine1_next_state <= 3'd5;
			end
		end
		2'd3: begin
			if (litedramcore_bankmachine1_trccon_ready) begin
				if (litedramcore_bankmachine1_cmd_ready) begin
					bankmachine1_next_state <= 3'd7;
				end
			end
		end
		3'd4: begin
			if ((~litedramcore_bankmachine1_refresh_req)) begin
				bankmachine1_next_state <= 1'd0;
			end
		end
		3'd5: begin
			bankmachine1_next_state <= 3'd6;
		end
		3'd6: begin
			bankmachine1_next_state <= 2'd3;
		end
		3'd7: begin
			bankmachine1_next_state <= 4'd8;
		end
		4'd8: begin
			bankmachine1_next_state <= 1'd0;
		end
		default: begin
			if (litedramcore_bankmachine1_refresh_req) begin
				bankmachine1_next_state <= 3'd4;
			end else begin
				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine1_row_opened) begin
						if (litedramcore_bankmachine1_row_hit) begin
							if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
								bankmachine1_next_state <= 2'd2;
							end
						end else begin
							bankmachine1_next_state <= 1'd1;
						end
					end else begin
						bankmachine1_next_state <= 2'd3;
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_139 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_140;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine1_row_open <= 1'd0;
	case (bankmachine1_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine1_trccon_ready) begin
				litedramcore_bankmachine1_row_open <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_140 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_141;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine1_row_close <= 1'd0;
	case (bankmachine1_state)
		1'd1: begin
			litedramcore_bankmachine1_row_close <= 1'd1;
		end
		2'd2: begin
			litedramcore_bankmachine1_row_close <= 1'd1;
		end
		2'd3: begin
		end
		3'd4: begin
			litedramcore_bankmachine1_row_close <= 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_141 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_142;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
	case (bankmachine1_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine1_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine1_row_opened) begin
						if (litedramcore_bankmachine1_row_hit) begin
							litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_142 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_143;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
	case (bankmachine1_state)
		1'd1: begin
			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
				litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine1_trccon_ready) begin
				litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_143 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_144;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
	case (bankmachine1_state)
		1'd1: begin
			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
				litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine1_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine1_row_opened) begin
						if (litedramcore_bankmachine1_row_hit) begin
							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_144 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_145;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
	case (bankmachine1_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine1_trccon_ready) begin
				litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_145 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_146;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
	case (bankmachine1_state)
		1'd1: begin
			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
				litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine1_trccon_ready) begin
				litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
			end
		end
		3'd4: begin
			litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_146 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_147;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
	case (bankmachine1_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine1_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine1_row_opened) begin
						if (litedramcore_bankmachine1_row_hit) begin
							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_147 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_148;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
	case (bankmachine1_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine1_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine1_row_opened) begin
						if (litedramcore_bankmachine1_row_hit) begin
							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_148 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_149;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
	case (bankmachine1_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine1_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine1_row_opened) begin
						if (litedramcore_bankmachine1_row_hit) begin
							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_149 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_150;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
	case (bankmachine1_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine1_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine1_row_opened) begin
						if (litedramcore_bankmachine1_row_hit) begin
							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_150 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_151;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine1_refresh_gnt <= 1'd0;
	case (bankmachine1_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
			if (litedramcore_bankmachine1_twtpcon_ready) begin
				litedramcore_bankmachine1_refresh_gnt <= 1'd1;
			end
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_151 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_152;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine1_cmd_valid <= 1'd0;
	case (bankmachine1_state)
		1'd1: begin
			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
				litedramcore_bankmachine1_cmd_valid <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine1_trccon_ready) begin
				litedramcore_bankmachine1_cmd_valid <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine1_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine1_row_opened) begin
						if (litedramcore_bankmachine1_row_hit) begin
							litedramcore_bankmachine1_cmd_valid <= 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_152 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid;
assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr;
assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready;
assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid);
assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]);
assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2;

// synthesis translate_off
reg dummy_d_153;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine2_cmd_payload_a <= 15'd0;
	if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
		litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7];
	end else begin
		litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
	end
// synthesis translate_off
	dummy_d_153 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write);
assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);

// synthesis translate_off
reg dummy_d_154;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine2_auto_precharge <= 1'd0;
	if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
		if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7])) begin
			litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
		end
	end
// synthesis translate_off
	dummy_d_154 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;

// synthesis translate_off
reg dummy_d_155;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
	if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
		litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
	end else begin
		litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
	end
// synthesis translate_off
	dummy_d_155 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready);

// synthesis translate_off
reg dummy_d_156;
// synthesis translate_on
always @(*) begin
	bankmachine2_next_state <= 4'd0;
	bankmachine2_next_state <= bankmachine2_state;
	case (bankmachine2_state)
		1'd1: begin
			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
				if (litedramcore_bankmachine2_cmd_ready) begin
					bankmachine2_next_state <= 3'd5;
				end
			end
		end
		2'd2: begin
			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
				bankmachine2_next_state <= 3'd5;
			end
		end
		2'd3: begin
			if (litedramcore_bankmachine2_trccon_ready) begin
				if (litedramcore_bankmachine2_cmd_ready) begin
					bankmachine2_next_state <= 3'd7;
				end
			end
		end
		3'd4: begin
			if ((~litedramcore_bankmachine2_refresh_req)) begin
				bankmachine2_next_state <= 1'd0;
			end
		end
		3'd5: begin
			bankmachine2_next_state <= 3'd6;
		end
		3'd6: begin
			bankmachine2_next_state <= 2'd3;
		end
		3'd7: begin
			bankmachine2_next_state <= 4'd8;
		end
		4'd8: begin
			bankmachine2_next_state <= 1'd0;
		end
		default: begin
			if (litedramcore_bankmachine2_refresh_req) begin
				bankmachine2_next_state <= 3'd4;
			end else begin
				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine2_row_opened) begin
						if (litedramcore_bankmachine2_row_hit) begin
							if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
								bankmachine2_next_state <= 2'd2;
							end
						end else begin
							bankmachine2_next_state <= 1'd1;
						end
					end else begin
						bankmachine2_next_state <= 2'd3;
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_156 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_157;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine2_row_open <= 1'd0;
	case (bankmachine2_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine2_trccon_ready) begin
				litedramcore_bankmachine2_row_open <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_157 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_158;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine2_row_close <= 1'd0;
	case (bankmachine2_state)
		1'd1: begin
			litedramcore_bankmachine2_row_close <= 1'd1;
		end
		2'd2: begin
			litedramcore_bankmachine2_row_close <= 1'd1;
		end
		2'd3: begin
		end
		3'd4: begin
			litedramcore_bankmachine2_row_close <= 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_158 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_159;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
	case (bankmachine2_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine2_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine2_row_opened) begin
						if (litedramcore_bankmachine2_row_hit) begin
							litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_159 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_160;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
	case (bankmachine2_state)
		1'd1: begin
			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
				litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine2_trccon_ready) begin
				litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_160 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_161;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
	case (bankmachine2_state)
		1'd1: begin
			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
				litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine2_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine2_row_opened) begin
						if (litedramcore_bankmachine2_row_hit) begin
							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_161 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_162;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
	case (bankmachine2_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine2_trccon_ready) begin
				litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_162 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_163;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
	case (bankmachine2_state)
		1'd1: begin
			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
				litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine2_trccon_ready) begin
				litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
			end
		end
		3'd4: begin
			litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_163 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_164;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
	case (bankmachine2_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine2_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine2_row_opened) begin
						if (litedramcore_bankmachine2_row_hit) begin
							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_164 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_165;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
	case (bankmachine2_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine2_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine2_row_opened) begin
						if (litedramcore_bankmachine2_row_hit) begin
							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_165 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_166;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
	case (bankmachine2_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine2_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine2_row_opened) begin
						if (litedramcore_bankmachine2_row_hit) begin
							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_166 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_167;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
	case (bankmachine2_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine2_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine2_row_opened) begin
						if (litedramcore_bankmachine2_row_hit) begin
							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_167 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_168;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine2_refresh_gnt <= 1'd0;
	case (bankmachine2_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
			if (litedramcore_bankmachine2_twtpcon_ready) begin
				litedramcore_bankmachine2_refresh_gnt <= 1'd1;
			end
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_168 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_169;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine2_cmd_valid <= 1'd0;
	case (bankmachine2_state)
		1'd1: begin
			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
				litedramcore_bankmachine2_cmd_valid <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine2_trccon_ready) begin
				litedramcore_bankmachine2_cmd_valid <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine2_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine2_row_opened) begin
						if (litedramcore_bankmachine2_row_hit) begin
							litedramcore_bankmachine2_cmd_valid <= 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_169 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid;
assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr;
assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready;
assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid);
assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]);
assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3;

// synthesis translate_off
reg dummy_d_170;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine3_cmd_payload_a <= 15'd0;
	if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
		litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7];
	end else begin
		litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
	end
// synthesis translate_off
	dummy_d_170 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write);
assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);

// synthesis translate_off
reg dummy_d_171;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine3_auto_precharge <= 1'd0;
	if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
		if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7])) begin
			litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
		end
	end
// synthesis translate_off
	dummy_d_171 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;

// synthesis translate_off
reg dummy_d_172;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
	if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
		litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
	end else begin
		litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
	end
// synthesis translate_off
	dummy_d_172 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready);

// synthesis translate_off
reg dummy_d_173;
// synthesis translate_on
always @(*) begin
	bankmachine3_next_state <= 4'd0;
	bankmachine3_next_state <= bankmachine3_state;
	case (bankmachine3_state)
		1'd1: begin
			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
				if (litedramcore_bankmachine3_cmd_ready) begin
					bankmachine3_next_state <= 3'd5;
				end
			end
		end
		2'd2: begin
			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
				bankmachine3_next_state <= 3'd5;
			end
		end
		2'd3: begin
			if (litedramcore_bankmachine3_trccon_ready) begin
				if (litedramcore_bankmachine3_cmd_ready) begin
					bankmachine3_next_state <= 3'd7;
				end
			end
		end
		3'd4: begin
			if ((~litedramcore_bankmachine3_refresh_req)) begin
				bankmachine3_next_state <= 1'd0;
			end
		end
		3'd5: begin
			bankmachine3_next_state <= 3'd6;
		end
		3'd6: begin
			bankmachine3_next_state <= 2'd3;
		end
		3'd7: begin
			bankmachine3_next_state <= 4'd8;
		end
		4'd8: begin
			bankmachine3_next_state <= 1'd0;
		end
		default: begin
			if (litedramcore_bankmachine3_refresh_req) begin
				bankmachine3_next_state <= 3'd4;
			end else begin
				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine3_row_opened) begin
						if (litedramcore_bankmachine3_row_hit) begin
							if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
								bankmachine3_next_state <= 2'd2;
							end
						end else begin
							bankmachine3_next_state <= 1'd1;
						end
					end else begin
						bankmachine3_next_state <= 2'd3;
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_173 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_174;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine3_row_open <= 1'd0;
	case (bankmachine3_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine3_trccon_ready) begin
				litedramcore_bankmachine3_row_open <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_174 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_175;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine3_row_close <= 1'd0;
	case (bankmachine3_state)
		1'd1: begin
			litedramcore_bankmachine3_row_close <= 1'd1;
		end
		2'd2: begin
			litedramcore_bankmachine3_row_close <= 1'd1;
		end
		2'd3: begin
		end
		3'd4: begin
			litedramcore_bankmachine3_row_close <= 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_175 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_176;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
	case (bankmachine3_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine3_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine3_row_opened) begin
						if (litedramcore_bankmachine3_row_hit) begin
							litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_176 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_177;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
	case (bankmachine3_state)
		1'd1: begin
			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
				litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine3_trccon_ready) begin
				litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_177 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_178;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
	case (bankmachine3_state)
		1'd1: begin
			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
				litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine3_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine3_row_opened) begin
						if (litedramcore_bankmachine3_row_hit) begin
							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_178 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_179;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
	case (bankmachine3_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine3_trccon_ready) begin
				litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_179 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_180;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
	case (bankmachine3_state)
		1'd1: begin
			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
				litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine3_trccon_ready) begin
				litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
			end
		end
		3'd4: begin
			litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_180 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_181;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
	case (bankmachine3_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine3_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine3_row_opened) begin
						if (litedramcore_bankmachine3_row_hit) begin
							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_181 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_182;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
	case (bankmachine3_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine3_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine3_row_opened) begin
						if (litedramcore_bankmachine3_row_hit) begin
							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_182 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_183;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
	case (bankmachine3_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine3_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine3_row_opened) begin
						if (litedramcore_bankmachine3_row_hit) begin
							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_183 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_184;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
	case (bankmachine3_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine3_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine3_row_opened) begin
						if (litedramcore_bankmachine3_row_hit) begin
							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_184 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_185;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine3_refresh_gnt <= 1'd0;
	case (bankmachine3_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
			if (litedramcore_bankmachine3_twtpcon_ready) begin
				litedramcore_bankmachine3_refresh_gnt <= 1'd1;
			end
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_185 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_186;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine3_cmd_valid <= 1'd0;
	case (bankmachine3_state)
		1'd1: begin
			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
				litedramcore_bankmachine3_cmd_valid <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine3_trccon_ready) begin
				litedramcore_bankmachine3_cmd_valid <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine3_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine3_row_opened) begin
						if (litedramcore_bankmachine3_row_hit) begin
							litedramcore_bankmachine3_cmd_valid <= 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_186 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid;
assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr;
assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready;
assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid);
assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]);
assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4;

// synthesis translate_off
reg dummy_d_187;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine4_cmd_payload_a <= 15'd0;
	if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
		litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7];
	end else begin
		litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
	end
// synthesis translate_off
	dummy_d_187 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write);
assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);

// synthesis translate_off
reg dummy_d_188;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine4_auto_precharge <= 1'd0;
	if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
		if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7])) begin
			litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
		end
	end
// synthesis translate_off
	dummy_d_188 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;

// synthesis translate_off
reg dummy_d_189;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
	if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
		litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
	end else begin
		litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
	end
// synthesis translate_off
	dummy_d_189 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready);

// synthesis translate_off
reg dummy_d_190;
// synthesis translate_on
always @(*) begin
	bankmachine4_next_state <= 4'd0;
	bankmachine4_next_state <= bankmachine4_state;
	case (bankmachine4_state)
		1'd1: begin
			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
				if (litedramcore_bankmachine4_cmd_ready) begin
					bankmachine4_next_state <= 3'd5;
				end
			end
		end
		2'd2: begin
			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
				bankmachine4_next_state <= 3'd5;
			end
		end
		2'd3: begin
			if (litedramcore_bankmachine4_trccon_ready) begin
				if (litedramcore_bankmachine4_cmd_ready) begin
					bankmachine4_next_state <= 3'd7;
				end
			end
		end
		3'd4: begin
			if ((~litedramcore_bankmachine4_refresh_req)) begin
				bankmachine4_next_state <= 1'd0;
			end
		end
		3'd5: begin
			bankmachine4_next_state <= 3'd6;
		end
		3'd6: begin
			bankmachine4_next_state <= 2'd3;
		end
		3'd7: begin
			bankmachine4_next_state <= 4'd8;
		end
		4'd8: begin
			bankmachine4_next_state <= 1'd0;
		end
		default: begin
			if (litedramcore_bankmachine4_refresh_req) begin
				bankmachine4_next_state <= 3'd4;
			end else begin
				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine4_row_opened) begin
						if (litedramcore_bankmachine4_row_hit) begin
							if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
								bankmachine4_next_state <= 2'd2;
							end
						end else begin
							bankmachine4_next_state <= 1'd1;
						end
					end else begin
						bankmachine4_next_state <= 2'd3;
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_190 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_191;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine4_row_open <= 1'd0;
	case (bankmachine4_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine4_trccon_ready) begin
				litedramcore_bankmachine4_row_open <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_191 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_192;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine4_row_close <= 1'd0;
	case (bankmachine4_state)
		1'd1: begin
			litedramcore_bankmachine4_row_close <= 1'd1;
		end
		2'd2: begin
			litedramcore_bankmachine4_row_close <= 1'd1;
		end
		2'd3: begin
		end
		3'd4: begin
			litedramcore_bankmachine4_row_close <= 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_192 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_193;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
	case (bankmachine4_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine4_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine4_row_opened) begin
						if (litedramcore_bankmachine4_row_hit) begin
							litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_193 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_194;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
	case (bankmachine4_state)
		1'd1: begin
			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
				litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine4_trccon_ready) begin
				litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_194 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_195;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
	case (bankmachine4_state)
		1'd1: begin
			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
				litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine4_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine4_row_opened) begin
						if (litedramcore_bankmachine4_row_hit) begin
							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_195 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_196;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
	case (bankmachine4_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine4_trccon_ready) begin
				litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_196 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_197;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
	case (bankmachine4_state)
		1'd1: begin
			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
				litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine4_trccon_ready) begin
				litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
			end
		end
		3'd4: begin
			litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_197 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_198;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
	case (bankmachine4_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine4_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine4_row_opened) begin
						if (litedramcore_bankmachine4_row_hit) begin
							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_198 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_199;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
	case (bankmachine4_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine4_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine4_row_opened) begin
						if (litedramcore_bankmachine4_row_hit) begin
							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_199 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_200;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
	case (bankmachine4_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine4_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine4_row_opened) begin
						if (litedramcore_bankmachine4_row_hit) begin
							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_200 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_201;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
	case (bankmachine4_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine4_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine4_row_opened) begin
						if (litedramcore_bankmachine4_row_hit) begin
							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_201 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_202;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine4_refresh_gnt <= 1'd0;
	case (bankmachine4_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
			if (litedramcore_bankmachine4_twtpcon_ready) begin
				litedramcore_bankmachine4_refresh_gnt <= 1'd1;
			end
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_202 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_203;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine4_cmd_valid <= 1'd0;
	case (bankmachine4_state)
		1'd1: begin
			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
				litedramcore_bankmachine4_cmd_valid <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine4_trccon_ready) begin
				litedramcore_bankmachine4_cmd_valid <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine4_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine4_row_opened) begin
						if (litedramcore_bankmachine4_row_hit) begin
							litedramcore_bankmachine4_cmd_valid <= 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_203 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid;
assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr;
assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready;
assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid);
assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]);
assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5;

// synthesis translate_off
reg dummy_d_204;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine5_cmd_payload_a <= 15'd0;
	if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
		litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7];
	end else begin
		litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
	end
// synthesis translate_off
	dummy_d_204 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write);
assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);

// synthesis translate_off
reg dummy_d_205;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine5_auto_precharge <= 1'd0;
	if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
		if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7])) begin
			litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
		end
	end
// synthesis translate_off
	dummy_d_205 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;

// synthesis translate_off
reg dummy_d_206;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
	if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
		litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
	end else begin
		litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
	end
// synthesis translate_off
	dummy_d_206 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready);

// synthesis translate_off
reg dummy_d_207;
// synthesis translate_on
always @(*) begin
	bankmachine5_next_state <= 4'd0;
	bankmachine5_next_state <= bankmachine5_state;
	case (bankmachine5_state)
		1'd1: begin
			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
				if (litedramcore_bankmachine5_cmd_ready) begin
					bankmachine5_next_state <= 3'd5;
				end
			end
		end
		2'd2: begin
			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
				bankmachine5_next_state <= 3'd5;
			end
		end
		2'd3: begin
			if (litedramcore_bankmachine5_trccon_ready) begin
				if (litedramcore_bankmachine5_cmd_ready) begin
					bankmachine5_next_state <= 3'd7;
				end
			end
		end
		3'd4: begin
			if ((~litedramcore_bankmachine5_refresh_req)) begin
				bankmachine5_next_state <= 1'd0;
			end
		end
		3'd5: begin
			bankmachine5_next_state <= 3'd6;
		end
		3'd6: begin
			bankmachine5_next_state <= 2'd3;
		end
		3'd7: begin
			bankmachine5_next_state <= 4'd8;
		end
		4'd8: begin
			bankmachine5_next_state <= 1'd0;
		end
		default: begin
			if (litedramcore_bankmachine5_refresh_req) begin
				bankmachine5_next_state <= 3'd4;
			end else begin
				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine5_row_opened) begin
						if (litedramcore_bankmachine5_row_hit) begin
							if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
								bankmachine5_next_state <= 2'd2;
							end
						end else begin
							bankmachine5_next_state <= 1'd1;
						end
					end else begin
						bankmachine5_next_state <= 2'd3;
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_207 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_208;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine5_row_open <= 1'd0;
	case (bankmachine5_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine5_trccon_ready) begin
				litedramcore_bankmachine5_row_open <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_208 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_209;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine5_row_close <= 1'd0;
	case (bankmachine5_state)
		1'd1: begin
			litedramcore_bankmachine5_row_close <= 1'd1;
		end
		2'd2: begin
			litedramcore_bankmachine5_row_close <= 1'd1;
		end
		2'd3: begin
		end
		3'd4: begin
			litedramcore_bankmachine5_row_close <= 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_209 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_210;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
	case (bankmachine5_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine5_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine5_row_opened) begin
						if (litedramcore_bankmachine5_row_hit) begin
							litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_210 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_211;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
	case (bankmachine5_state)
		1'd1: begin
			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
				litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine5_trccon_ready) begin
				litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_211 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_212;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
	case (bankmachine5_state)
		1'd1: begin
			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
				litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine5_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine5_row_opened) begin
						if (litedramcore_bankmachine5_row_hit) begin
							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_212 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_213;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
	case (bankmachine5_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine5_trccon_ready) begin
				litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_213 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_214;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
	case (bankmachine5_state)
		1'd1: begin
			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
				litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine5_trccon_ready) begin
				litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
			end
		end
		3'd4: begin
			litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_214 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_215;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
	case (bankmachine5_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine5_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine5_row_opened) begin
						if (litedramcore_bankmachine5_row_hit) begin
							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_215 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_216;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
	case (bankmachine5_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine5_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine5_row_opened) begin
						if (litedramcore_bankmachine5_row_hit) begin
							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_216 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_217;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
	case (bankmachine5_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine5_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine5_row_opened) begin
						if (litedramcore_bankmachine5_row_hit) begin
							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_217 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_218;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
	case (bankmachine5_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine5_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine5_row_opened) begin
						if (litedramcore_bankmachine5_row_hit) begin
							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_218 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_219;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine5_refresh_gnt <= 1'd0;
	case (bankmachine5_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
			if (litedramcore_bankmachine5_twtpcon_ready) begin
				litedramcore_bankmachine5_refresh_gnt <= 1'd1;
			end
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_219 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_220;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine5_cmd_valid <= 1'd0;
	case (bankmachine5_state)
		1'd1: begin
			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
				litedramcore_bankmachine5_cmd_valid <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine5_trccon_ready) begin
				litedramcore_bankmachine5_cmd_valid <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine5_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine5_row_opened) begin
						if (litedramcore_bankmachine5_row_hit) begin
							litedramcore_bankmachine5_cmd_valid <= 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_220 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid;
assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr;
assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready;
assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid);
assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]);
assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6;

// synthesis translate_off
reg dummy_d_221;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine6_cmd_payload_a <= 15'd0;
	if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
		litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7];
	end else begin
		litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
	end
// synthesis translate_off
	dummy_d_221 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write);
assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);

// synthesis translate_off
reg dummy_d_222;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine6_auto_precharge <= 1'd0;
	if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
		if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7])) begin
			litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
		end
	end
// synthesis translate_off
	dummy_d_222 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;

// synthesis translate_off
reg dummy_d_223;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
	if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
		litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
	end else begin
		litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
	end
// synthesis translate_off
	dummy_d_223 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready);

// synthesis translate_off
reg dummy_d_224;
// synthesis translate_on
always @(*) begin
	bankmachine6_next_state <= 4'd0;
	bankmachine6_next_state <= bankmachine6_state;
	case (bankmachine6_state)
		1'd1: begin
			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
				if (litedramcore_bankmachine6_cmd_ready) begin
					bankmachine6_next_state <= 3'd5;
				end
			end
		end
		2'd2: begin
			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
				bankmachine6_next_state <= 3'd5;
			end
		end
		2'd3: begin
			if (litedramcore_bankmachine6_trccon_ready) begin
				if (litedramcore_bankmachine6_cmd_ready) begin
					bankmachine6_next_state <= 3'd7;
				end
			end
		end
		3'd4: begin
			if ((~litedramcore_bankmachine6_refresh_req)) begin
				bankmachine6_next_state <= 1'd0;
			end
		end
		3'd5: begin
			bankmachine6_next_state <= 3'd6;
		end
		3'd6: begin
			bankmachine6_next_state <= 2'd3;
		end
		3'd7: begin
			bankmachine6_next_state <= 4'd8;
		end
		4'd8: begin
			bankmachine6_next_state <= 1'd0;
		end
		default: begin
			if (litedramcore_bankmachine6_refresh_req) begin
				bankmachine6_next_state <= 3'd4;
			end else begin
				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine6_row_opened) begin
						if (litedramcore_bankmachine6_row_hit) begin
							if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
								bankmachine6_next_state <= 2'd2;
							end
						end else begin
							bankmachine6_next_state <= 1'd1;
						end
					end else begin
						bankmachine6_next_state <= 2'd3;
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_224 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_225;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine6_row_open <= 1'd0;
	case (bankmachine6_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine6_trccon_ready) begin
				litedramcore_bankmachine6_row_open <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_225 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_226;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine6_row_close <= 1'd0;
	case (bankmachine6_state)
		1'd1: begin
			litedramcore_bankmachine6_row_close <= 1'd1;
		end
		2'd2: begin
			litedramcore_bankmachine6_row_close <= 1'd1;
		end
		2'd3: begin
		end
		3'd4: begin
			litedramcore_bankmachine6_row_close <= 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_226 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_227;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
	case (bankmachine6_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine6_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine6_row_opened) begin
						if (litedramcore_bankmachine6_row_hit) begin
							litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_227 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_228;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
	case (bankmachine6_state)
		1'd1: begin
			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
				litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine6_trccon_ready) begin
				litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_228 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_229;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
	case (bankmachine6_state)
		1'd1: begin
			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
				litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine6_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine6_row_opened) begin
						if (litedramcore_bankmachine6_row_hit) begin
							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_229 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_230;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
	case (bankmachine6_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine6_trccon_ready) begin
				litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_230 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_231;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
	case (bankmachine6_state)
		1'd1: begin
			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
				litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine6_trccon_ready) begin
				litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
			end
		end
		3'd4: begin
			litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_231 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_232;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
	case (bankmachine6_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine6_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine6_row_opened) begin
						if (litedramcore_bankmachine6_row_hit) begin
							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_232 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_233;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
	case (bankmachine6_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine6_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine6_row_opened) begin
						if (litedramcore_bankmachine6_row_hit) begin
							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_233 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_234;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
	case (bankmachine6_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine6_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine6_row_opened) begin
						if (litedramcore_bankmachine6_row_hit) begin
							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_234 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_235;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
	case (bankmachine6_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine6_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine6_row_opened) begin
						if (litedramcore_bankmachine6_row_hit) begin
							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_235 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_236;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine6_refresh_gnt <= 1'd0;
	case (bankmachine6_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
			if (litedramcore_bankmachine6_twtpcon_ready) begin
				litedramcore_bankmachine6_refresh_gnt <= 1'd1;
			end
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_236 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_237;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine6_cmd_valid <= 1'd0;
	case (bankmachine6_state)
		1'd1: begin
			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
				litedramcore_bankmachine6_cmd_valid <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine6_trccon_ready) begin
				litedramcore_bankmachine6_cmd_valid <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine6_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine6_row_opened) begin
						if (litedramcore_bankmachine6_row_hit) begin
							litedramcore_bankmachine6_cmd_valid <= 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_237 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid;
assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr;
assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready;
assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid);
assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]);
assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7;

// synthesis translate_off
reg dummy_d_238;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine7_cmd_payload_a <= 15'd0;
	if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
		litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7];
	end else begin
		litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
	end
// synthesis translate_off
	dummy_d_238 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write);
assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);

// synthesis translate_off
reg dummy_d_239;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine7_auto_precharge <= 1'd0;
	if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
		if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7])) begin
			litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
		end
	end
// synthesis translate_off
	dummy_d_239 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;

// synthesis translate_off
reg dummy_d_240;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
	if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
		litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
	end else begin
		litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
	end
// synthesis translate_off
	dummy_d_240 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready);

// synthesis translate_off
reg dummy_d_241;
// synthesis translate_on
always @(*) begin
	bankmachine7_next_state <= 4'd0;
	bankmachine7_next_state <= bankmachine7_state;
	case (bankmachine7_state)
		1'd1: begin
			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
				if (litedramcore_bankmachine7_cmd_ready) begin
					bankmachine7_next_state <= 3'd5;
				end
			end
		end
		2'd2: begin
			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
				bankmachine7_next_state <= 3'd5;
			end
		end
		2'd3: begin
			if (litedramcore_bankmachine7_trccon_ready) begin
				if (litedramcore_bankmachine7_cmd_ready) begin
					bankmachine7_next_state <= 3'd7;
				end
			end
		end
		3'd4: begin
			if ((~litedramcore_bankmachine7_refresh_req)) begin
				bankmachine7_next_state <= 1'd0;
			end
		end
		3'd5: begin
			bankmachine7_next_state <= 3'd6;
		end
		3'd6: begin
			bankmachine7_next_state <= 2'd3;
		end
		3'd7: begin
			bankmachine7_next_state <= 4'd8;
		end
		4'd8: begin
			bankmachine7_next_state <= 1'd0;
		end
		default: begin
			if (litedramcore_bankmachine7_refresh_req) begin
				bankmachine7_next_state <= 3'd4;
			end else begin
				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine7_row_opened) begin
						if (litedramcore_bankmachine7_row_hit) begin
							if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
								bankmachine7_next_state <= 2'd2;
							end
						end else begin
							bankmachine7_next_state <= 1'd1;
						end
					end else begin
						bankmachine7_next_state <= 2'd3;
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_241 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_242;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine7_row_open <= 1'd0;
	case (bankmachine7_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine7_trccon_ready) begin
				litedramcore_bankmachine7_row_open <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_242 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_243;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine7_row_close <= 1'd0;
	case (bankmachine7_state)
		1'd1: begin
			litedramcore_bankmachine7_row_close <= 1'd1;
		end
		2'd2: begin
			litedramcore_bankmachine7_row_close <= 1'd1;
		end
		2'd3: begin
		end
		3'd4: begin
			litedramcore_bankmachine7_row_close <= 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_243 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_244;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
	case (bankmachine7_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine7_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine7_row_opened) begin
						if (litedramcore_bankmachine7_row_hit) begin
							litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_244 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_245;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
	case (bankmachine7_state)
		1'd1: begin
			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
				litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine7_trccon_ready) begin
				litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_245 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_246;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
	case (bankmachine7_state)
		1'd1: begin
			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
				litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine7_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine7_row_opened) begin
						if (litedramcore_bankmachine7_row_hit) begin
							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_246 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_247;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
	case (bankmachine7_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine7_trccon_ready) begin
				litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_247 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_248;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
	case (bankmachine7_state)
		1'd1: begin
			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
				litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine7_trccon_ready) begin
				litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
			end
		end
		3'd4: begin
			litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_248 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_249;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
	case (bankmachine7_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine7_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine7_row_opened) begin
						if (litedramcore_bankmachine7_row_hit) begin
							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_249 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_250;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
	case (bankmachine7_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine7_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine7_row_opened) begin
						if (litedramcore_bankmachine7_row_hit) begin
							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_250 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_251;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
	case (bankmachine7_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine7_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine7_row_opened) begin
						if (litedramcore_bankmachine7_row_hit) begin
							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_251 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_252;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
	case (bankmachine7_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine7_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine7_row_opened) begin
						if (litedramcore_bankmachine7_row_hit) begin
							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_252 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_253;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine7_refresh_gnt <= 1'd0;
	case (bankmachine7_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
			if (litedramcore_bankmachine7_twtpcon_ready) begin
				litedramcore_bankmachine7_refresh_gnt <= 1'd1;
			end
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_253 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_254;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine7_cmd_valid <= 1'd0;
	case (bankmachine7_state)
		1'd1: begin
			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
				litedramcore_bankmachine7_cmd_valid <= 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine7_trccon_ready) begin
				litedramcore_bankmachine7_cmd_valid <= 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine7_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine7_row_opened) begin
						if (litedramcore_bankmachine7_row_hit) begin
							litedramcore_bankmachine7_cmd_valid <= 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
// synthesis translate_off
	dummy_d_254 = dummy_s;
// synthesis translate_on
end
assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready);
assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read));
assign litedramcore_cas_allowed = litedramcore_tccdcon_ready;
assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read));
assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write));
assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0);
assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0);
assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid;
assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid;
assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid;
assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid;
assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid;
assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid;
assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid;
assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid;
assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt);
assign litedramcore_interface_rdata = {litedramcore_dfi_p3_rddata, litedramcore_dfi_p2_rddata, litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata};
assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);

// synthesis translate_off
reg dummy_d_255;
// synthesis translate_on
always @(*) begin
	litedramcore_choose_cmd_valids <= 8'd0;
	litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
	litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
	litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
	litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
	litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
	litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
	litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
	litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
// synthesis translate_off
	dummy_d_255 = dummy_s;
// synthesis translate_on
end
assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1;
assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2;
assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3;
assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;

// synthesis translate_off
reg dummy_d_256;
// synthesis translate_on
always @(*) begin
	litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
	if (litedramcore_choose_cmd_cmd_valid) begin
		litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
	end
// synthesis translate_off
	dummy_d_256 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_257;
// synthesis translate_on
always @(*) begin
	litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
	if (litedramcore_choose_cmd_cmd_valid) begin
		litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
	end
// synthesis translate_off
	dummy_d_257 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_258;
// synthesis translate_on
always @(*) begin
	litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
	if (litedramcore_choose_cmd_cmd_valid) begin
		litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
	end
// synthesis translate_off
	dummy_d_258 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_259;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine0_cmd_ready <= 1'd0;
	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
		litedramcore_bankmachine0_cmd_ready <= 1'd1;
	end
	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
		litedramcore_bankmachine0_cmd_ready <= 1'd1;
	end
// synthesis translate_off
	dummy_d_259 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_260;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine1_cmd_ready <= 1'd0;
	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
		litedramcore_bankmachine1_cmd_ready <= 1'd1;
	end
	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
		litedramcore_bankmachine1_cmd_ready <= 1'd1;
	end
// synthesis translate_off
	dummy_d_260 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_261;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine2_cmd_ready <= 1'd0;
	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
		litedramcore_bankmachine2_cmd_ready <= 1'd1;
	end
	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
		litedramcore_bankmachine2_cmd_ready <= 1'd1;
	end
// synthesis translate_off
	dummy_d_261 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_262;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine3_cmd_ready <= 1'd0;
	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
		litedramcore_bankmachine3_cmd_ready <= 1'd1;
	end
	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
		litedramcore_bankmachine3_cmd_ready <= 1'd1;
	end
// synthesis translate_off
	dummy_d_262 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_263;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine4_cmd_ready <= 1'd0;
	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
		litedramcore_bankmachine4_cmd_ready <= 1'd1;
	end
	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
		litedramcore_bankmachine4_cmd_ready <= 1'd1;
	end
// synthesis translate_off
	dummy_d_263 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_264;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine5_cmd_ready <= 1'd0;
	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
		litedramcore_bankmachine5_cmd_ready <= 1'd1;
	end
	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
		litedramcore_bankmachine5_cmd_ready <= 1'd1;
	end
// synthesis translate_off
	dummy_d_264 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_265;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine6_cmd_ready <= 1'd0;
	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
		litedramcore_bankmachine6_cmd_ready <= 1'd1;
	end
	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
		litedramcore_bankmachine6_cmd_ready <= 1'd1;
	end
// synthesis translate_off
	dummy_d_265 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_266;
// synthesis translate_on
always @(*) begin
	litedramcore_bankmachine7_cmd_ready <= 1'd0;
	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
		litedramcore_bankmachine7_cmd_ready <= 1'd1;
	end
	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
		litedramcore_bankmachine7_cmd_ready <= 1'd1;
	end
// synthesis translate_off
	dummy_d_266 = dummy_s;
// synthesis translate_on
end
assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid));

// synthesis translate_off
reg dummy_d_267;
// synthesis translate_on
always @(*) begin
	litedramcore_choose_req_valids <= 8'd0;
	litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
	litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
	litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
	litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
	litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
	litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
	litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
	litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
// synthesis translate_off
	dummy_d_267 = dummy_s;
// synthesis translate_on
end
assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7;
assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8;
assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9;
assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;

// synthesis translate_off
reg dummy_d_268;
// synthesis translate_on
always @(*) begin
	litedramcore_choose_req_cmd_payload_cas <= 1'd0;
	if (litedramcore_choose_req_cmd_valid) begin
		litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
	end
// synthesis translate_off
	dummy_d_268 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_269;
// synthesis translate_on
always @(*) begin
	litedramcore_choose_req_cmd_payload_ras <= 1'd0;
	if (litedramcore_choose_req_cmd_valid) begin
		litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
	end
// synthesis translate_off
	dummy_d_269 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_270;
// synthesis translate_on
always @(*) begin
	litedramcore_choose_req_cmd_payload_we <= 1'd0;
	if (litedramcore_choose_req_cmd_valid) begin
		litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
	end
// synthesis translate_off
	dummy_d_270 = dummy_s;
// synthesis translate_on
end
assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
assign litedramcore_dfi_p0_reset_n = 1'd1;
assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}};
assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}};
assign litedramcore_dfi_p1_reset_n = 1'd1;
assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}};
assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}};
assign litedramcore_dfi_p2_reset_n = 1'd1;
assign litedramcore_dfi_p2_cke = {1{litedramcore_steerer4}};
assign litedramcore_dfi_p2_odt = {1{litedramcore_steerer5}};
assign litedramcore_dfi_p3_reset_n = 1'd1;
assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}};
assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}};
assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]);

// synthesis translate_off
reg dummy_d_271;
// synthesis translate_on
always @(*) begin
	multiplexer_next_state <= 4'd0;
	multiplexer_next_state <= multiplexer_state;
	case (multiplexer_state)
		1'd1: begin
			if (litedramcore_read_available) begin
				if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
					multiplexer_next_state <= 2'd3;
				end
			end
			if (litedramcore_go_to_refresh) begin
				multiplexer_next_state <= 2'd2;
			end
		end
		2'd2: begin
			if (litedramcore_cmd_last) begin
				multiplexer_next_state <= 1'd0;
			end
		end
		2'd3: begin
			if (litedramcore_twtrcon_ready) begin
				multiplexer_next_state <= 1'd0;
			end
		end
		3'd4: begin
			multiplexer_next_state <= 3'd5;
		end
		3'd5: begin
			multiplexer_next_state <= 3'd6;
		end
		3'd6: begin
			multiplexer_next_state <= 3'd7;
		end
		3'd7: begin
			multiplexer_next_state <= 4'd8;
		end
		4'd8: begin
			multiplexer_next_state <= 4'd9;
		end
		4'd9: begin
			multiplexer_next_state <= 4'd10;
		end
		4'd10: begin
			multiplexer_next_state <= 1'd1;
		end
		default: begin
			if (litedramcore_write_available) begin
				if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
					multiplexer_next_state <= 3'd4;
				end
			end
			if (litedramcore_go_to_refresh) begin
				multiplexer_next_state <= 2'd2;
			end
		end
	endcase
// synthesis translate_off
	dummy_d_271 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_272;
// synthesis translate_on
always @(*) begin
	litedramcore_choose_req_cmd_ready <= 1'd0;
	case (multiplexer_state)
		1'd1: begin
			if (1'd0) begin
				litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
			end else begin
				litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
			end
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		4'd9: begin
		end
		4'd10: begin
		end
		default: begin
			if (1'd0) begin
				litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
			end else begin
				litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
			end
		end
	endcase
// synthesis translate_off
	dummy_d_272 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_273;
// synthesis translate_on
always @(*) begin
	litedramcore_en1 <= 1'd0;
	case (multiplexer_state)
		1'd1: begin
			litedramcore_en1 <= 1'd1;
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		4'd9: begin
		end
		4'd10: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_273 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_274;
// synthesis translate_on
always @(*) begin
	litedramcore_steerer_sel0 <= 2'd0;
	case (multiplexer_state)
		1'd1: begin
			litedramcore_steerer_sel0 <= 1'd0;
		end
		2'd2: begin
			litedramcore_steerer_sel0 <= 2'd3;
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		4'd9: begin
		end
		4'd10: begin
		end
		default: begin
			litedramcore_steerer_sel0 <= 1'd0;
		end
	endcase
// synthesis translate_off
	dummy_d_274 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_275;
// synthesis translate_on
always @(*) begin
	litedramcore_steerer_sel1 <= 2'd0;
	case (multiplexer_state)
		1'd1: begin
			litedramcore_steerer_sel1 <= 1'd0;
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		4'd9: begin
		end
		4'd10: begin
		end
		default: begin
			litedramcore_steerer_sel1 <= 1'd1;
		end
	endcase
// synthesis translate_off
	dummy_d_275 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_276;
// synthesis translate_on
always @(*) begin
	litedramcore_steerer_sel2 <= 2'd0;
	case (multiplexer_state)
		1'd1: begin
			litedramcore_steerer_sel2 <= 1'd1;
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		4'd9: begin
		end
		4'd10: begin
		end
		default: begin
			litedramcore_steerer_sel2 <= 2'd2;
		end
	endcase
// synthesis translate_off
	dummy_d_276 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_277;
// synthesis translate_on
always @(*) begin
	litedramcore_choose_cmd_want_activates <= 1'd0;
	case (multiplexer_state)
		1'd1: begin
			if (1'd0) begin
			end else begin
				litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
			end
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		4'd9: begin
		end
		4'd10: begin
		end
		default: begin
			if (1'd0) begin
			end else begin
				litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
			end
		end
	endcase
// synthesis translate_off
	dummy_d_277 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_278;
// synthesis translate_on
always @(*) begin
	litedramcore_steerer_sel3 <= 2'd0;
	case (multiplexer_state)
		1'd1: begin
			litedramcore_steerer_sel3 <= 2'd2;
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		4'd9: begin
		end
		4'd10: begin
		end
		default: begin
			litedramcore_steerer_sel3 <= 1'd0;
		end
	endcase
// synthesis translate_off
	dummy_d_278 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_279;
// synthesis translate_on
always @(*) begin
	litedramcore_en0 <= 1'd0;
	case (multiplexer_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		4'd9: begin
		end
		4'd10: begin
		end
		default: begin
			litedramcore_en0 <= 1'd1;
		end
	endcase
// synthesis translate_off
	dummy_d_279 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_280;
// synthesis translate_on
always @(*) begin
	litedramcore_cmd_ready <= 1'd0;
	case (multiplexer_state)
		1'd1: begin
		end
		2'd2: begin
			litedramcore_cmd_ready <= 1'd1;
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		4'd9: begin
		end
		4'd10: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_280 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_281;
// synthesis translate_on
always @(*) begin
	litedramcore_choose_cmd_cmd_ready <= 1'd0;
	case (multiplexer_state)
		1'd1: begin
			if (1'd0) begin
			end else begin
				litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
			end
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		4'd9: begin
		end
		4'd10: begin
		end
		default: begin
			if (1'd0) begin
			end else begin
				litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
			end
		end
	endcase
// synthesis translate_off
	dummy_d_281 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_282;
// synthesis translate_on
always @(*) begin
	litedramcore_choose_req_want_reads <= 1'd0;
	case (multiplexer_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		4'd9: begin
		end
		4'd10: begin
		end
		default: begin
			litedramcore_choose_req_want_reads <= 1'd1;
		end
	endcase
// synthesis translate_off
	dummy_d_282 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_283;
// synthesis translate_on
always @(*) begin
	litedramcore_choose_req_want_writes <= 1'd0;
	case (multiplexer_state)
		1'd1: begin
			litedramcore_choose_req_want_writes <= 1'd1;
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		4'd9: begin
		end
		4'd10: begin
		end
		default: begin
		end
	endcase
// synthesis translate_off
	dummy_d_283 = dummy_s;
// synthesis translate_on
end
assign roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
assign litedramcore_interface_bank0_addr = rhs_array_muxed12;
assign litedramcore_interface_bank0_we = rhs_array_muxed13;
assign litedramcore_interface_bank0_valid = rhs_array_muxed14;
assign roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock));
assign litedramcore_interface_bank1_addr = rhs_array_muxed15;
assign litedramcore_interface_bank1_we = rhs_array_muxed16;
assign litedramcore_interface_bank1_valid = rhs_array_muxed17;
assign roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock));
assign litedramcore_interface_bank2_addr = rhs_array_muxed18;
assign litedramcore_interface_bank2_we = rhs_array_muxed19;
assign litedramcore_interface_bank2_valid = rhs_array_muxed20;
assign roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock));
assign litedramcore_interface_bank3_addr = rhs_array_muxed21;
assign litedramcore_interface_bank3_we = rhs_array_muxed22;
assign litedramcore_interface_bank3_valid = rhs_array_muxed23;
assign roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock));
assign litedramcore_interface_bank4_addr = rhs_array_muxed24;
assign litedramcore_interface_bank4_we = rhs_array_muxed25;
assign litedramcore_interface_bank4_valid = rhs_array_muxed26;
assign roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock));
assign litedramcore_interface_bank5_addr = rhs_array_muxed27;
assign litedramcore_interface_bank5_we = rhs_array_muxed28;
assign litedramcore_interface_bank5_valid = rhs_array_muxed29;
assign roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock));
assign litedramcore_interface_bank6_addr = rhs_array_muxed30;
assign litedramcore_interface_bank6_we = rhs_array_muxed31;
assign litedramcore_interface_bank6_valid = rhs_array_muxed32;
assign roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)};
assign roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock));
assign litedramcore_interface_bank7_addr = rhs_array_muxed33;
assign litedramcore_interface_bank7_we = rhs_array_muxed34;
assign litedramcore_interface_bank7_valid = rhs_array_muxed35;
assign user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready));
assign user_port_wdata_ready = new_master_wdata_ready2;
assign user_port_rdata_valid = new_master_rdata_valid8;

// synthesis translate_off
reg dummy_d_284;
// synthesis translate_on
always @(*) begin
	litedramcore_interface_wdata <= 128'd0;
	case ({new_master_wdata_ready2})
		1'd1: begin
			litedramcore_interface_wdata <= user_port_wdata_payload_data;
		end
		default: begin
			litedramcore_interface_wdata <= 1'd0;
		end
	endcase
// synthesis translate_off
	dummy_d_284 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_285;
// synthesis translate_on
always @(*) begin
	litedramcore_interface_wdata_we <= 16'd0;
	case ({new_master_wdata_ready2})
		1'd1: begin
			litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
		end
		default: begin
			litedramcore_interface_wdata_we <= 1'd0;
		end
	endcase
// synthesis translate_off
	dummy_d_285 = dummy_s;
// synthesis translate_on
end
assign user_port_rdata_payload_data = litedramcore_interface_rdata;
assign roundrobin0_grant = 1'd0;
assign roundrobin1_grant = 1'd0;
assign roundrobin2_grant = 1'd0;
assign roundrobin3_grant = 1'd0;
assign roundrobin4_grant = 1'd0;
assign roundrobin5_grant = 1'd0;
assign roundrobin6_grant = 1'd0;
assign roundrobin7_grant = 1'd0;
assign litedramcore_wishbone_adr = wb_bus_adr;
assign litedramcore_wishbone_dat_w = wb_bus_dat_w;
assign wb_bus_dat_r = litedramcore_wishbone_dat_r;
assign litedramcore_wishbone_sel = wb_bus_sel;
assign litedramcore_wishbone_cyc = wb_bus_cyc;
assign litedramcore_wishbone_stb = wb_bus_stb;
assign wb_bus_ack = litedramcore_wishbone_ack;
assign litedramcore_wishbone_we = wb_bus_we;
assign litedramcore_wishbone_cti = wb_bus_cti;
assign litedramcore_wishbone_bte = wb_bus_bte;
assign wb_bus_err = litedramcore_wishbone_err;

// synthesis translate_off
reg dummy_d_286;
// synthesis translate_on
always @(*) begin
	csrbank0_sel <= 1'd0;
	csrbank0_sel <= (interface0_bank_bus_adr[13:9] == 2'd2);
	if (interface0_bank_bus_adr[0]) begin
		csrbank0_sel <= 1'd0;
	end
// synthesis translate_off
	dummy_d_286 = dummy_s;
// synthesis translate_on
end
assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd0));
assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd0));
assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd1));
assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd1));
assign csrbank0_init_done0_w = init_done_storage;
assign csrbank0_init_error0_w = init_error_storage;

// synthesis translate_off
reg dummy_d_287;
// synthesis translate_on
always @(*) begin
	csrbank1_sel <= 1'd0;
	csrbank1_sel <= (interface1_bank_bus_adr[13:9] == 1'd0);
	if (interface1_bank_bus_adr[0]) begin
		csrbank1_sel <= 1'd0;
	end
// synthesis translate_off
	dummy_d_287 = dummy_s;
// synthesis translate_on
end
assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0];
assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd0));
assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd0));
assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0];
assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd1));
assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd1));
assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0];
assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd2));
assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd2));
assign a7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0];
assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd3));
assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd3));
assign a7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0];
assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd4));
assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd4));
assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd5));
assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd5));
assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd6));
assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd6));
assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd7));
assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd7));
assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd8));
assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd8));
assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd9));
assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd9));
assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0];
assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage;
assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0];

// synthesis translate_off
reg dummy_d_288;
// synthesis translate_on
always @(*) begin
	csrbank2_sel <= 1'd0;
	csrbank2_sel <= (interface2_bank_bus_adr[13:9] == 1'd1);
	if (interface2_bank_bus_adr[0]) begin
		csrbank2_sel <= 1'd0;
	end
// synthesis translate_off
	dummy_d_288 = dummy_s;
// synthesis translate_on
end
assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd0));
assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd0));
assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd1));
assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd1));
assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd2));
assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd2));
assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0];
assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd3));
assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd3));
assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd4));
assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd4));
assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd5));
assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd5));
assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0];
assign csrbank2_dfii_pi0_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd6));
assign csrbank2_dfii_pi0_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd6));
assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd7));
assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd7));
assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd8));
assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd8));
assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0];
assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd9));
assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd9));
assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd10));
assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd10));
assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd11));
assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd11));
assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0];
assign csrbank2_dfii_pi1_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd12));
assign csrbank2_dfii_pi1_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd12));
assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0];
assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd13));
assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd13));
assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0];
assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd14));
assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd14));
assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[14:0];
assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd15));
assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd15));
assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0];
assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd16));
assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd16));
assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0];
assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd17));
assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd17));
assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0];
assign csrbank2_dfii_pi2_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd18));
assign csrbank2_dfii_pi2_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd18));
assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0];
assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd19));
assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd19));
assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0];
assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd20));
assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd20));
assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[14:0];
assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd21));
assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd21));
assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0];
assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd22));
assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd22));
assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0];
assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd23));
assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd23));
assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0];
assign csrbank2_dfii_pi3_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd24));
assign csrbank2_dfii_pi3_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd24));
assign csrbank2_dfii_control0_w = litedramcore_storage[3:0];
assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[14:0];
assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0];
assign csrbank2_dfii_pi0_rddata_w = litedramcore_phaseinjector0_status[31:0];
assign litedramcore_phaseinjector0_we = csrbank2_dfii_pi0_rddata_we;
assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[14:0];
assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0];
assign csrbank2_dfii_pi1_rddata_w = litedramcore_phaseinjector1_status[31:0];
assign litedramcore_phaseinjector1_we = csrbank2_dfii_pi1_rddata_we;
assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0];
assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[14:0];
assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0];
assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0];
assign csrbank2_dfii_pi2_rddata_w = litedramcore_phaseinjector2_status[31:0];
assign litedramcore_phaseinjector2_we = csrbank2_dfii_pi2_rddata_we;
assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0];
assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[14:0];
assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0];
assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0];
assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0];
assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata_we;
assign adr = litedramcore_adr;
assign we = litedramcore_we;
assign dat_w = litedramcore_dat_w;
assign litedramcore_dat_r = dat_r;
assign interface0_bank_bus_adr = adr;
assign interface1_bank_bus_adr = adr;
assign interface2_bank_bus_adr = adr;
assign interface0_bank_bus_we = we;
assign interface1_bank_bus_we = we;
assign interface2_bank_bus_we = we;
assign interface0_bank_bus_dat_w = dat_w;
assign interface1_bank_bus_dat_w = dat_w;
assign interface2_bank_bus_dat_w = dat_w;
assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);

// synthesis translate_off
reg dummy_d_289;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed0 <= 1'd0;
	case (litedramcore_choose_cmd_grant)
		1'd0: begin
			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
		end
		1'd1: begin
			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
		end
		2'd2: begin
			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
		end
		2'd3: begin
			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
		end
		3'd4: begin
			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
		end
		3'd5: begin
			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
		end
		3'd6: begin
			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
		end
		default: begin
			rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
		end
	endcase
// synthesis translate_off
	dummy_d_289 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_290;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed1 <= 15'd0;
	case (litedramcore_choose_cmd_grant)
		1'd0: begin
			rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
		end
		1'd1: begin
			rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
		end
		2'd2: begin
			rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
		end
		2'd3: begin
			rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
		end
		3'd4: begin
			rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
		end
		3'd5: begin
			rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
		end
		3'd6: begin
			rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
		end
		default: begin
			rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
		end
	endcase
// synthesis translate_off
	dummy_d_290 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_291;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed2 <= 3'd0;
	case (litedramcore_choose_cmd_grant)
		1'd0: begin
			rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
		end
		1'd1: begin
			rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
		end
		2'd2: begin
			rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
		end
		2'd3: begin
			rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
		end
		3'd4: begin
			rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
		end
		3'd5: begin
			rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
		end
		3'd6: begin
			rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
		end
		default: begin
			rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
		end
	endcase
// synthesis translate_off
	dummy_d_291 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_292;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed3 <= 1'd0;
	case (litedramcore_choose_cmd_grant)
		1'd0: begin
			rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
		end
		1'd1: begin
			rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
		end
		2'd2: begin
			rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
		end
		2'd3: begin
			rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
		end
		3'd4: begin
			rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
		end
		3'd5: begin
			rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
		end
		3'd6: begin
			rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
		end
		default: begin
			rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
		end
	endcase
// synthesis translate_off
	dummy_d_292 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_293;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed4 <= 1'd0;
	case (litedramcore_choose_cmd_grant)
		1'd0: begin
			rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
		end
		1'd1: begin
			rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
		end
		2'd2: begin
			rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
		end
		2'd3: begin
			rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
		end
		3'd4: begin
			rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
		end
		3'd5: begin
			rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
		end
		3'd6: begin
			rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
		end
		default: begin
			rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
		end
	endcase
// synthesis translate_off
	dummy_d_293 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_294;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed5 <= 1'd0;
	case (litedramcore_choose_cmd_grant)
		1'd0: begin
			rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
		end
		1'd1: begin
			rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
		end
		2'd2: begin
			rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
		end
		2'd3: begin
			rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
		end
		3'd4: begin
			rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
		end
		3'd5: begin
			rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
		end
		3'd6: begin
			rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
		end
		default: begin
			rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
		end
	endcase
// synthesis translate_off
	dummy_d_294 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_295;
// synthesis translate_on
always @(*) begin
	t_array_muxed0 <= 1'd0;
	case (litedramcore_choose_cmd_grant)
		1'd0: begin
			t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
		end
		1'd1: begin
			t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
		end
		2'd2: begin
			t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
		end
		2'd3: begin
			t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
		end
		3'd4: begin
			t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
		end
		3'd5: begin
			t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
		end
		3'd6: begin
			t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
		end
		default: begin
			t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
		end
	endcase
// synthesis translate_off
	dummy_d_295 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_296;
// synthesis translate_on
always @(*) begin
	t_array_muxed1 <= 1'd0;
	case (litedramcore_choose_cmd_grant)
		1'd0: begin
			t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
		end
		1'd1: begin
			t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
		end
		2'd2: begin
			t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
		end
		2'd3: begin
			t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
		end
		3'd4: begin
			t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
		end
		3'd5: begin
			t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
		end
		3'd6: begin
			t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
		end
		default: begin
			t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
		end
	endcase
// synthesis translate_off
	dummy_d_296 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_297;
// synthesis translate_on
always @(*) begin
	t_array_muxed2 <= 1'd0;
	case (litedramcore_choose_cmd_grant)
		1'd0: begin
			t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
		end
		1'd1: begin
			t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
		end
		2'd2: begin
			t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
		end
		2'd3: begin
			t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
		end
		3'd4: begin
			t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
		end
		3'd5: begin
			t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
		end
		3'd6: begin
			t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
		end
		default: begin
			t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
		end
	endcase
// synthesis translate_off
	dummy_d_297 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_298;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed6 <= 1'd0;
	case (litedramcore_choose_req_grant)
		1'd0: begin
			rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
		end
		1'd1: begin
			rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
		end
		2'd2: begin
			rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
		end
		2'd3: begin
			rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
		end
		3'd4: begin
			rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
		end
		3'd5: begin
			rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
		end
		3'd6: begin
			rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
		end
		default: begin
			rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
		end
	endcase
// synthesis translate_off
	dummy_d_298 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_299;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed7 <= 15'd0;
	case (litedramcore_choose_req_grant)
		1'd0: begin
			rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
		end
		1'd1: begin
			rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
		end
		2'd2: begin
			rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
		end
		2'd3: begin
			rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
		end
		3'd4: begin
			rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
		end
		3'd5: begin
			rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
		end
		3'd6: begin
			rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
		end
		default: begin
			rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
		end
	endcase
// synthesis translate_off
	dummy_d_299 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_300;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed8 <= 3'd0;
	case (litedramcore_choose_req_grant)
		1'd0: begin
			rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
		end
		1'd1: begin
			rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
		end
		2'd2: begin
			rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
		end
		2'd3: begin
			rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
		end
		3'd4: begin
			rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
		end
		3'd5: begin
			rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
		end
		3'd6: begin
			rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
		end
		default: begin
			rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
		end
	endcase
// synthesis translate_off
	dummy_d_300 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_301;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed9 <= 1'd0;
	case (litedramcore_choose_req_grant)
		1'd0: begin
			rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
		end
		1'd1: begin
			rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
		end
		2'd2: begin
			rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
		end
		2'd3: begin
			rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
		end
		3'd4: begin
			rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
		end
		3'd5: begin
			rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
		end
		3'd6: begin
			rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
		end
		default: begin
			rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
		end
	endcase
// synthesis translate_off
	dummy_d_301 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_302;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed10 <= 1'd0;
	case (litedramcore_choose_req_grant)
		1'd0: begin
			rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
		end
		1'd1: begin
			rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
		end
		2'd2: begin
			rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
		end
		2'd3: begin
			rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
		end
		3'd4: begin
			rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
		end
		3'd5: begin
			rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
		end
		3'd6: begin
			rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
		end
		default: begin
			rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
		end
	endcase
// synthesis translate_off
	dummy_d_302 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_303;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed11 <= 1'd0;
	case (litedramcore_choose_req_grant)
		1'd0: begin
			rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
		end
		1'd1: begin
			rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
		end
		2'd2: begin
			rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
		end
		2'd3: begin
			rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
		end
		3'd4: begin
			rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
		end
		3'd5: begin
			rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
		end
		3'd6: begin
			rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
		end
		default: begin
			rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
		end
	endcase
// synthesis translate_off
	dummy_d_303 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_304;
// synthesis translate_on
always @(*) begin
	t_array_muxed3 <= 1'd0;
	case (litedramcore_choose_req_grant)
		1'd0: begin
			t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
		end
		1'd1: begin
			t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
		end
		2'd2: begin
			t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
		end
		2'd3: begin
			t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
		end
		3'd4: begin
			t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
		end
		3'd5: begin
			t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
		end
		3'd6: begin
			t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
		end
		default: begin
			t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
		end
	endcase
// synthesis translate_off
	dummy_d_304 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_305;
// synthesis translate_on
always @(*) begin
	t_array_muxed4 <= 1'd0;
	case (litedramcore_choose_req_grant)
		1'd0: begin
			t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
		end
		1'd1: begin
			t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
		end
		2'd2: begin
			t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
		end
		2'd3: begin
			t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
		end
		3'd4: begin
			t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
		end
		3'd5: begin
			t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
		end
		3'd6: begin
			t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
		end
		default: begin
			t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
		end
	endcase
// synthesis translate_off
	dummy_d_305 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_306;
// synthesis translate_on
always @(*) begin
	t_array_muxed5 <= 1'd0;
	case (litedramcore_choose_req_grant)
		1'd0: begin
			t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
		end
		1'd1: begin
			t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
		end
		2'd2: begin
			t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
		end
		2'd3: begin
			t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
		end
		3'd4: begin
			t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
		end
		3'd5: begin
			t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
		end
		3'd6: begin
			t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
		end
		default: begin
			t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
		end
	endcase
// synthesis translate_off
	dummy_d_306 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_307;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed12 <= 22'd0;
	case (roundrobin0_grant)
		default: begin
			rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
		end
	endcase
// synthesis translate_off
	dummy_d_307 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_308;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed13 <= 1'd0;
	case (roundrobin0_grant)
		default: begin
			rhs_array_muxed13 <= user_port_cmd_payload_we;
		end
	endcase
// synthesis translate_off
	dummy_d_308 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_309;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed14 <= 1'd0;
	case (roundrobin0_grant)
		default: begin
			rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
		end
	endcase
// synthesis translate_off
	dummy_d_309 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_310;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed15 <= 22'd0;
	case (roundrobin1_grant)
		default: begin
			rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
		end
	endcase
// synthesis translate_off
	dummy_d_310 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_311;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed16 <= 1'd0;
	case (roundrobin1_grant)
		default: begin
			rhs_array_muxed16 <= user_port_cmd_payload_we;
		end
	endcase
// synthesis translate_off
	dummy_d_311 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_312;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed17 <= 1'd0;
	case (roundrobin1_grant)
		default: begin
			rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
		end
	endcase
// synthesis translate_off
	dummy_d_312 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_313;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed18 <= 22'd0;
	case (roundrobin2_grant)
		default: begin
			rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
		end
	endcase
// synthesis translate_off
	dummy_d_313 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_314;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed19 <= 1'd0;
	case (roundrobin2_grant)
		default: begin
			rhs_array_muxed19 <= user_port_cmd_payload_we;
		end
	endcase
// synthesis translate_off
	dummy_d_314 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_315;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed20 <= 1'd0;
	case (roundrobin2_grant)
		default: begin
			rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
		end
	endcase
// synthesis translate_off
	dummy_d_315 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_316;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed21 <= 22'd0;
	case (roundrobin3_grant)
		default: begin
			rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
		end
	endcase
// synthesis translate_off
	dummy_d_316 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_317;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed22 <= 1'd0;
	case (roundrobin3_grant)
		default: begin
			rhs_array_muxed22 <= user_port_cmd_payload_we;
		end
	endcase
// synthesis translate_off
	dummy_d_317 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_318;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed23 <= 1'd0;
	case (roundrobin3_grant)
		default: begin
			rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
		end
	endcase
// synthesis translate_off
	dummy_d_318 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_319;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed24 <= 22'd0;
	case (roundrobin4_grant)
		default: begin
			rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
		end
	endcase
// synthesis translate_off
	dummy_d_319 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_320;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed25 <= 1'd0;
	case (roundrobin4_grant)
		default: begin
			rhs_array_muxed25 <= user_port_cmd_payload_we;
		end
	endcase
// synthesis translate_off
	dummy_d_320 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_321;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed26 <= 1'd0;
	case (roundrobin4_grant)
		default: begin
			rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
		end
	endcase
// synthesis translate_off
	dummy_d_321 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_322;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed27 <= 22'd0;
	case (roundrobin5_grant)
		default: begin
			rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
		end
	endcase
// synthesis translate_off
	dummy_d_322 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_323;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed28 <= 1'd0;
	case (roundrobin5_grant)
		default: begin
			rhs_array_muxed28 <= user_port_cmd_payload_we;
		end
	endcase
// synthesis translate_off
	dummy_d_323 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_324;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed29 <= 1'd0;
	case (roundrobin5_grant)
		default: begin
			rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
		end
	endcase
// synthesis translate_off
	dummy_d_324 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_325;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed30 <= 22'd0;
	case (roundrobin6_grant)
		default: begin
			rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
		end
	endcase
// synthesis translate_off
	dummy_d_325 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_326;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed31 <= 1'd0;
	case (roundrobin6_grant)
		default: begin
			rhs_array_muxed31 <= user_port_cmd_payload_we;
		end
	endcase
// synthesis translate_off
	dummy_d_326 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_327;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed32 <= 1'd0;
	case (roundrobin6_grant)
		default: begin
			rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
		end
	endcase
// synthesis translate_off
	dummy_d_327 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_328;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed33 <= 22'd0;
	case (roundrobin7_grant)
		default: begin
			rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
		end
	endcase
// synthesis translate_off
	dummy_d_328 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_329;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed34 <= 1'd0;
	case (roundrobin7_grant)
		default: begin
			rhs_array_muxed34 <= user_port_cmd_payload_we;
		end
	endcase
// synthesis translate_off
	dummy_d_329 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_330;
// synthesis translate_on
always @(*) begin
	rhs_array_muxed35 <= 1'd0;
	case (roundrobin7_grant)
		default: begin
			rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
		end
	endcase
// synthesis translate_off
	dummy_d_330 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_331;
// synthesis translate_on
always @(*) begin
	array_muxed0 <= 3'd0;
	case (litedramcore_steerer_sel0)
		1'd0: begin
			array_muxed0 <= litedramcore_nop_ba[2:0];
		end
		1'd1: begin
			array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
		end
		2'd2: begin
			array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
		end
		default: begin
			array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
		end
	endcase
// synthesis translate_off
	dummy_d_331 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_332;
// synthesis translate_on
always @(*) begin
	array_muxed1 <= 15'd0;
	case (litedramcore_steerer_sel0)
		1'd0: begin
			array_muxed1 <= litedramcore_nop_a;
		end
		1'd1: begin
			array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
		end
		2'd2: begin
			array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
		end
		default: begin
			array_muxed1 <= litedramcore_cmd_payload_a;
		end
	endcase
// synthesis translate_off
	dummy_d_332 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_333;
// synthesis translate_on
always @(*) begin
	array_muxed2 <= 1'd0;
	case (litedramcore_steerer_sel0)
		1'd0: begin
			array_muxed2 <= 1'd0;
		end
		1'd1: begin
			array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
		end
		2'd2: begin
			array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
		end
		default: begin
			array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
		end
	endcase
// synthesis translate_off
	dummy_d_333 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_334;
// synthesis translate_on
always @(*) begin
	array_muxed3 <= 1'd0;
	case (litedramcore_steerer_sel0)
		1'd0: begin
			array_muxed3 <= 1'd0;
		end
		1'd1: begin
			array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
		end
		2'd2: begin
			array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
		end
		default: begin
			array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
		end
	endcase
// synthesis translate_off
	dummy_d_334 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_335;
// synthesis translate_on
always @(*) begin
	array_muxed4 <= 1'd0;
	case (litedramcore_steerer_sel0)
		1'd0: begin
			array_muxed4 <= 1'd0;
		end
		1'd1: begin
			array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
		end
		2'd2: begin
			array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
		end
		default: begin
			array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
		end
	endcase
// synthesis translate_off
	dummy_d_335 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_336;
// synthesis translate_on
always @(*) begin
	array_muxed5 <= 1'd0;
	case (litedramcore_steerer_sel0)
		1'd0: begin
			array_muxed5 <= 1'd0;
		end
		1'd1: begin
			array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
		end
		2'd2: begin
			array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
		end
		default: begin
			array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
		end
	endcase
// synthesis translate_off
	dummy_d_336 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_337;
// synthesis translate_on
always @(*) begin
	array_muxed6 <= 1'd0;
	case (litedramcore_steerer_sel0)
		1'd0: begin
			array_muxed6 <= 1'd0;
		end
		1'd1: begin
			array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
		end
		2'd2: begin
			array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
		end
		default: begin
			array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
		end
	endcase
// synthesis translate_off
	dummy_d_337 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_338;
// synthesis translate_on
always @(*) begin
	array_muxed7 <= 3'd0;
	case (litedramcore_steerer_sel1)
		1'd0: begin
			array_muxed7 <= litedramcore_nop_ba[2:0];
		end
		1'd1: begin
			array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
		end
		2'd2: begin
			array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
		end
		default: begin
			array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
		end
	endcase
// synthesis translate_off
	dummy_d_338 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_339;
// synthesis translate_on
always @(*) begin
	array_muxed8 <= 15'd0;
	case (litedramcore_steerer_sel1)
		1'd0: begin
			array_muxed8 <= litedramcore_nop_a;
		end
		1'd1: begin
			array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
		end
		2'd2: begin
			array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
		end
		default: begin
			array_muxed8 <= litedramcore_cmd_payload_a;
		end
	endcase
// synthesis translate_off
	dummy_d_339 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_340;
// synthesis translate_on
always @(*) begin
	array_muxed9 <= 1'd0;
	case (litedramcore_steerer_sel1)
		1'd0: begin
			array_muxed9 <= 1'd0;
		end
		1'd1: begin
			array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
		end
		2'd2: begin
			array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
		end
		default: begin
			array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
		end
	endcase
// synthesis translate_off
	dummy_d_340 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_341;
// synthesis translate_on
always @(*) begin
	array_muxed10 <= 1'd0;
	case (litedramcore_steerer_sel1)
		1'd0: begin
			array_muxed10 <= 1'd0;
		end
		1'd1: begin
			array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
		end
		2'd2: begin
			array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
		end
		default: begin
			array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
		end
	endcase
// synthesis translate_off
	dummy_d_341 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_342;
// synthesis translate_on
always @(*) begin
	array_muxed11 <= 1'd0;
	case (litedramcore_steerer_sel1)
		1'd0: begin
			array_muxed11 <= 1'd0;
		end
		1'd1: begin
			array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
		end
		2'd2: begin
			array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
		end
		default: begin
			array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
		end
	endcase
// synthesis translate_off
	dummy_d_342 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_343;
// synthesis translate_on
always @(*) begin
	array_muxed12 <= 1'd0;
	case (litedramcore_steerer_sel1)
		1'd0: begin
			array_muxed12 <= 1'd0;
		end
		1'd1: begin
			array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
		end
		2'd2: begin
			array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
		end
		default: begin
			array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
		end
	endcase
// synthesis translate_off
	dummy_d_343 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_344;
// synthesis translate_on
always @(*) begin
	array_muxed13 <= 1'd0;
	case (litedramcore_steerer_sel1)
		1'd0: begin
			array_muxed13 <= 1'd0;
		end
		1'd1: begin
			array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
		end
		2'd2: begin
			array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
		end
		default: begin
			array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
		end
	endcase
// synthesis translate_off
	dummy_d_344 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_345;
// synthesis translate_on
always @(*) begin
	array_muxed14 <= 3'd0;
	case (litedramcore_steerer_sel2)
		1'd0: begin
			array_muxed14 <= litedramcore_nop_ba[2:0];
		end
		1'd1: begin
			array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
		end
		2'd2: begin
			array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0];
		end
		default: begin
			array_muxed14 <= litedramcore_cmd_payload_ba[2:0];
		end
	endcase
// synthesis translate_off
	dummy_d_345 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_346;
// synthesis translate_on
always @(*) begin
	array_muxed15 <= 15'd0;
	case (litedramcore_steerer_sel2)
		1'd0: begin
			array_muxed15 <= litedramcore_nop_a;
		end
		1'd1: begin
			array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a;
		end
		2'd2: begin
			array_muxed15 <= litedramcore_choose_req_cmd_payload_a;
		end
		default: begin
			array_muxed15 <= litedramcore_cmd_payload_a;
		end
	endcase
// synthesis translate_off
	dummy_d_346 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_347;
// synthesis translate_on
always @(*) begin
	array_muxed16 <= 1'd0;
	case (litedramcore_steerer_sel2)
		1'd0: begin
			array_muxed16 <= 1'd0;
		end
		1'd1: begin
			array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
		end
		2'd2: begin
			array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
		end
		default: begin
			array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
		end
	endcase
// synthesis translate_off
	dummy_d_347 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_348;
// synthesis translate_on
always @(*) begin
	array_muxed17 <= 1'd0;
	case (litedramcore_steerer_sel2)
		1'd0: begin
			array_muxed17 <= 1'd0;
		end
		1'd1: begin
			array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
		end
		2'd2: begin
			array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
		end
		default: begin
			array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
		end
	endcase
// synthesis translate_off
	dummy_d_348 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_349;
// synthesis translate_on
always @(*) begin
	array_muxed18 <= 1'd0;
	case (litedramcore_steerer_sel2)
		1'd0: begin
			array_muxed18 <= 1'd0;
		end
		1'd1: begin
			array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
		end
		2'd2: begin
			array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
		end
		default: begin
			array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
		end
	endcase
// synthesis translate_off
	dummy_d_349 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_350;
// synthesis translate_on
always @(*) begin
	array_muxed19 <= 1'd0;
	case (litedramcore_steerer_sel2)
		1'd0: begin
			array_muxed19 <= 1'd0;
		end
		1'd1: begin
			array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
		end
		2'd2: begin
			array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
		end
		default: begin
			array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
		end
	endcase
// synthesis translate_off
	dummy_d_350 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_351;
// synthesis translate_on
always @(*) begin
	array_muxed20 <= 1'd0;
	case (litedramcore_steerer_sel2)
		1'd0: begin
			array_muxed20 <= 1'd0;
		end
		1'd1: begin
			array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
		end
		2'd2: begin
			array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
		end
		default: begin
			array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
		end
	endcase
// synthesis translate_off
	dummy_d_351 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_352;
// synthesis translate_on
always @(*) begin
	array_muxed21 <= 3'd0;
	case (litedramcore_steerer_sel3)
		1'd0: begin
			array_muxed21 <= litedramcore_nop_ba[2:0];
		end
		1'd1: begin
			array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
		end
		2'd2: begin
			array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0];
		end
		default: begin
			array_muxed21 <= litedramcore_cmd_payload_ba[2:0];
		end
	endcase
// synthesis translate_off
	dummy_d_352 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_353;
// synthesis translate_on
always @(*) begin
	array_muxed22 <= 15'd0;
	case (litedramcore_steerer_sel3)
		1'd0: begin
			array_muxed22 <= litedramcore_nop_a;
		end
		1'd1: begin
			array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a;
		end
		2'd2: begin
			array_muxed22 <= litedramcore_choose_req_cmd_payload_a;
		end
		default: begin
			array_muxed22 <= litedramcore_cmd_payload_a;
		end
	endcase
// synthesis translate_off
	dummy_d_353 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_354;
// synthesis translate_on
always @(*) begin
	array_muxed23 <= 1'd0;
	case (litedramcore_steerer_sel3)
		1'd0: begin
			array_muxed23 <= 1'd0;
		end
		1'd1: begin
			array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
		end
		2'd2: begin
			array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
		end
		default: begin
			array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
		end
	endcase
// synthesis translate_off
	dummy_d_354 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_355;
// synthesis translate_on
always @(*) begin
	array_muxed24 <= 1'd0;
	case (litedramcore_steerer_sel3)
		1'd0: begin
			array_muxed24 <= 1'd0;
		end
		1'd1: begin
			array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
		end
		2'd2: begin
			array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
		end
		default: begin
			array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
		end
	endcase
// synthesis translate_off
	dummy_d_355 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_356;
// synthesis translate_on
always @(*) begin
	array_muxed25 <= 1'd0;
	case (litedramcore_steerer_sel3)
		1'd0: begin
			array_muxed25 <= 1'd0;
		end
		1'd1: begin
			array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
		end
		2'd2: begin
			array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
		end
		default: begin
			array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
		end
	endcase
// synthesis translate_off
	dummy_d_356 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_357;
// synthesis translate_on
always @(*) begin
	array_muxed26 <= 1'd0;
	case (litedramcore_steerer_sel3)
		1'd0: begin
			array_muxed26 <= 1'd0;
		end
		1'd1: begin
			array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
		end
		2'd2: begin
			array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
		end
		default: begin
			array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
		end
	endcase
// synthesis translate_off
	dummy_d_357 = dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_358;
// synthesis translate_on
always @(*) begin
	array_muxed27 <= 1'd0;
	case (litedramcore_steerer_sel3)
		1'd0: begin
			array_muxed27 <= 1'd0;
		end
		1'd1: begin
			array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
		end
		2'd2: begin
			array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
		end
		default: begin
			array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
		end
	endcase
// synthesis translate_off
	dummy_d_358 = dummy_s;
// synthesis translate_on
end
assign xilinxasyncresetsynchronizerimpl0 = ((~sys_pll_locked) | sys_pll_reset);
assign xilinxasyncresetsynchronizerimpl1 = ((~sys_pll_locked) | sys_pll_reset);
assign xilinxasyncresetsynchronizerimpl2 = ((~sys_pll_locked) | sys_pll_reset);
assign xilinxasyncresetsynchronizerimpl3 = ((~iodelay_pll_locked) | iodelay_pll_reset);

always @(posedge iodelay_clk) begin
	if ((reset_counter != 1'd0)) begin
		reset_counter <= (reset_counter - 1'd1);
	end else begin
		ic_reset <= 1'd0;
	end
	if (iodelay_rst) begin
		reset_counter <= 4'd15;
		ic_reset <= 1'd1;
	end
end

always @(posedge sys_clk) begin
	state <= next_state;
	a7ddrphy_dqs_oe_delayed <= ((a7ddrphy_dqspattern0 | a7ddrphy_dqs_oe) | a7ddrphy_dqspattern1);
	a7ddrphy_dq_oe_delayed <= ((a7ddrphy_dqspattern0 | a7ddrphy_dq_oe) | a7ddrphy_dqspattern1);
	a7ddrphy_rddata_en_last <= a7ddrphy_rddata_en;
	a7ddrphy_dfi_p0_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage);
	a7ddrphy_dfi_p1_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage);
	a7ddrphy_dfi_p2_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage);
	a7ddrphy_dfi_p3_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage);
	a7ddrphy_wrdata_en_last <= a7ddrphy_wrdata_en;
	a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0;
	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
		a7ddrphy_bitslip0_value <= (a7ddrphy_bitslip0_value + 1'd1);
	end
	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
		a7ddrphy_bitslip0_value <= 1'd0;
	end
	a7ddrphy_bitslip0_r <= {a7ddrphy_bitslip0_i, a7ddrphy_bitslip0_r[23:8]};
	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
		a7ddrphy_bitslip1_value <= (a7ddrphy_bitslip1_value + 1'd1);
	end
	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
		a7ddrphy_bitslip1_value <= 1'd0;
	end
	a7ddrphy_bitslip1_r <= {a7ddrphy_bitslip1_i, a7ddrphy_bitslip1_r[23:8]};
	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
		a7ddrphy_bitslip2_value <= (a7ddrphy_bitslip2_value + 1'd1);
	end
	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
		a7ddrphy_bitslip2_value <= 1'd0;
	end
	a7ddrphy_bitslip2_r <= {a7ddrphy_bitslip2_i, a7ddrphy_bitslip2_r[23:8]};
	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
		a7ddrphy_bitslip3_value <= (a7ddrphy_bitslip3_value + 1'd1);
	end
	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
		a7ddrphy_bitslip3_value <= 1'd0;
	end
	a7ddrphy_bitslip3_r <= {a7ddrphy_bitslip3_i, a7ddrphy_bitslip3_r[23:8]};
	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
		a7ddrphy_bitslip4_value <= (a7ddrphy_bitslip4_value + 1'd1);
	end
	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
		a7ddrphy_bitslip4_value <= 1'd0;
	end
	a7ddrphy_bitslip4_r <= {a7ddrphy_bitslip4_i, a7ddrphy_bitslip4_r[23:8]};
	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
		a7ddrphy_bitslip5_value <= (a7ddrphy_bitslip5_value + 1'd1);
	end
	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
		a7ddrphy_bitslip5_value <= 1'd0;
	end
	a7ddrphy_bitslip5_r <= {a7ddrphy_bitslip5_i, a7ddrphy_bitslip5_r[23:8]};
	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
		a7ddrphy_bitslip6_value <= (a7ddrphy_bitslip6_value + 1'd1);
	end
	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
		a7ddrphy_bitslip6_value <= 1'd0;
	end
	a7ddrphy_bitslip6_r <= {a7ddrphy_bitslip6_i, a7ddrphy_bitslip6_r[23:8]};
	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
		a7ddrphy_bitslip7_value <= (a7ddrphy_bitslip7_value + 1'd1);
	end
	if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
		a7ddrphy_bitslip7_value <= 1'd0;
	end
	a7ddrphy_bitslip7_r <= {a7ddrphy_bitslip7_i, a7ddrphy_bitslip7_r[23:8]};
	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
		a7ddrphy_bitslip8_value <= (a7ddrphy_bitslip8_value + 1'd1);
	end
	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
		a7ddrphy_bitslip8_value <= 1'd0;
	end
	a7ddrphy_bitslip8_r <= {a7ddrphy_bitslip8_i, a7ddrphy_bitslip8_r[23:8]};
	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
		a7ddrphy_bitslip9_value <= (a7ddrphy_bitslip9_value + 1'd1);
	end
	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
		a7ddrphy_bitslip9_value <= 1'd0;
	end
	a7ddrphy_bitslip9_r <= {a7ddrphy_bitslip9_i, a7ddrphy_bitslip9_r[23:8]};
	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
		a7ddrphy_bitslip10_value <= (a7ddrphy_bitslip10_value + 1'd1);
	end
	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
		a7ddrphy_bitslip10_value <= 1'd0;
	end
	a7ddrphy_bitslip10_r <= {a7ddrphy_bitslip10_i, a7ddrphy_bitslip10_r[23:8]};
	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
		a7ddrphy_bitslip11_value <= (a7ddrphy_bitslip11_value + 1'd1);
	end
	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
		a7ddrphy_bitslip11_value <= 1'd0;
	end
	a7ddrphy_bitslip11_r <= {a7ddrphy_bitslip11_i, a7ddrphy_bitslip11_r[23:8]};
	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
		a7ddrphy_bitslip12_value <= (a7ddrphy_bitslip12_value + 1'd1);
	end
	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
		a7ddrphy_bitslip12_value <= 1'd0;
	end
	a7ddrphy_bitslip12_r <= {a7ddrphy_bitslip12_i, a7ddrphy_bitslip12_r[23:8]};
	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
		a7ddrphy_bitslip13_value <= (a7ddrphy_bitslip13_value + 1'd1);
	end
	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
		a7ddrphy_bitslip13_value <= 1'd0;
	end
	a7ddrphy_bitslip13_r <= {a7ddrphy_bitslip13_i, a7ddrphy_bitslip13_r[23:8]};
	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
		a7ddrphy_bitslip14_value <= (a7ddrphy_bitslip14_value + 1'd1);
	end
	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
		a7ddrphy_bitslip14_value <= 1'd0;
	end
	a7ddrphy_bitslip14_r <= {a7ddrphy_bitslip14_i, a7ddrphy_bitslip14_r[23:8]};
	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
		a7ddrphy_bitslip15_value <= (a7ddrphy_bitslip15_value + 1'd1);
	end
	if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
		a7ddrphy_bitslip15_value <= 1'd0;
	end
	a7ddrphy_bitslip15_r <= {a7ddrphy_bitslip15_i, a7ddrphy_bitslip15_r[23:8]};
	if (litedramcore_inti_p0_rddata_valid) begin
		litedramcore_phaseinjector0_status <= litedramcore_inti_p0_rddata;
	end
	if (litedramcore_inti_p1_rddata_valid) begin
		litedramcore_phaseinjector1_status <= litedramcore_inti_p1_rddata;
	end
	if (litedramcore_inti_p2_rddata_valid) begin
		litedramcore_phaseinjector2_status <= litedramcore_inti_p2_rddata;
	end
	if (litedramcore_inti_p3_rddata_valid) begin
		litedramcore_phaseinjector3_status <= litedramcore_inti_p3_rddata;
	end
	if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
		litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
	end else begin
		litedramcore_timer_count1 <= 10'd781;
	end
	litedramcore_postponer_req_o <= 1'd0;
	if (litedramcore_postponer_req_i) begin
		litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
		if ((litedramcore_postponer_count == 1'd0)) begin
			litedramcore_postponer_count <= 1'd0;
			litedramcore_postponer_req_o <= 1'd1;
		end
	end
	if (litedramcore_sequencer_start0) begin
		litedramcore_sequencer_count <= 1'd0;
	end else begin
		if (litedramcore_sequencer_done1) begin
			if ((litedramcore_sequencer_count != 1'd0)) begin
				litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
			end
		end
	end
	litedramcore_cmd_payload_a <= 1'd0;
	litedramcore_cmd_payload_ba <= 1'd0;
	litedramcore_cmd_payload_cas <= 1'd0;
	litedramcore_cmd_payload_ras <= 1'd0;
	litedramcore_cmd_payload_we <= 1'd0;
	litedramcore_sequencer_done1 <= 1'd0;
	if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
		litedramcore_cmd_payload_a <= 11'd1024;
		litedramcore_cmd_payload_ba <= 1'd0;
		litedramcore_cmd_payload_cas <= 1'd0;
		litedramcore_cmd_payload_ras <= 1'd1;
		litedramcore_cmd_payload_we <= 1'd1;
	end
	if ((litedramcore_sequencer_counter == 2'd3)) begin
		litedramcore_cmd_payload_a <= 1'd0;
		litedramcore_cmd_payload_ba <= 1'd0;
		litedramcore_cmd_payload_cas <= 1'd1;
		litedramcore_cmd_payload_ras <= 1'd1;
		litedramcore_cmd_payload_we <= 1'd0;
	end
	if ((litedramcore_sequencer_counter == 6'd55)) begin
		litedramcore_cmd_payload_a <= 1'd0;
		litedramcore_cmd_payload_ba <= 1'd0;
		litedramcore_cmd_payload_cas <= 1'd0;
		litedramcore_cmd_payload_ras <= 1'd0;
		litedramcore_cmd_payload_we <= 1'd0;
		litedramcore_sequencer_done1 <= 1'd1;
	end
	if ((litedramcore_sequencer_counter == 6'd55)) begin
		litedramcore_sequencer_counter <= 1'd0;
	end else begin
		if ((litedramcore_sequencer_counter != 1'd0)) begin
			litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
		end else begin
			if (litedramcore_sequencer_start1) begin
				litedramcore_sequencer_counter <= 1'd1;
			end
		end
	end
	if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
		litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
	end else begin
		litedramcore_zqcs_timer_count1 <= 27'd99999999;
	end
	litedramcore_zqcs_executer_done <= 1'd0;
	if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
		litedramcore_cmd_payload_a <= 11'd1024;
		litedramcore_cmd_payload_ba <= 1'd0;
		litedramcore_cmd_payload_cas <= 1'd0;
		litedramcore_cmd_payload_ras <= 1'd1;
		litedramcore_cmd_payload_we <= 1'd1;
	end
	if ((litedramcore_zqcs_executer_counter == 2'd3)) begin
		litedramcore_cmd_payload_a <= 1'd0;
		litedramcore_cmd_payload_ba <= 1'd0;
		litedramcore_cmd_payload_cas <= 1'd0;
		litedramcore_cmd_payload_ras <= 1'd0;
		litedramcore_cmd_payload_we <= 1'd1;
	end
	if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
		litedramcore_cmd_payload_a <= 1'd0;
		litedramcore_cmd_payload_ba <= 1'd0;
		litedramcore_cmd_payload_cas <= 1'd0;
		litedramcore_cmd_payload_ras <= 1'd0;
		litedramcore_cmd_payload_we <= 1'd0;
		litedramcore_zqcs_executer_done <= 1'd1;
	end
	if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
		litedramcore_zqcs_executer_counter <= 1'd0;
	end else begin
		if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
			litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
		end else begin
			if (litedramcore_zqcs_executer_start) begin
				litedramcore_zqcs_executer_counter <= 1'd1;
			end
		end
	end
	refresher_state <= refresher_next_state;
	if (litedramcore_bankmachine0_row_close) begin
		litedramcore_bankmachine0_row_opened <= 1'd0;
	end else begin
		if (litedramcore_bankmachine0_row_open) begin
			litedramcore_bankmachine0_row_opened <= 1'd1;
			litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7];
		end
	end
	if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
		litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
	end
	if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
		litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
	end
	if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
		if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
			litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
		end
	end else begin
		if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
			litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
		end
	end
	if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
		litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid;
		litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first;
		litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last;
		litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
		litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
	end
	if (litedramcore_bankmachine0_twtpcon_valid) begin
		litedramcore_bankmachine0_twtpcon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
			litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
			if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
				litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine0_trccon_valid) begin
		litedramcore_bankmachine0_trccon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine0_trccon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine0_trccon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine0_trccon_ready)) begin
			litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
			if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
				litedramcore_bankmachine0_trccon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine0_trascon_valid) begin
		litedramcore_bankmachine0_trascon_count <= 3'd4;
		if (1'd0) begin
			litedramcore_bankmachine0_trascon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine0_trascon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine0_trascon_ready)) begin
			litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
			if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
				litedramcore_bankmachine0_trascon_ready <= 1'd1;
			end
		end
	end
	bankmachine0_state <= bankmachine0_next_state;
	if (litedramcore_bankmachine1_row_close) begin
		litedramcore_bankmachine1_row_opened <= 1'd0;
	end else begin
		if (litedramcore_bankmachine1_row_open) begin
			litedramcore_bankmachine1_row_opened <= 1'd1;
			litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7];
		end
	end
	if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
		litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
	end
	if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
		litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
	end
	if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
		if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
			litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
		end
	end else begin
		if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
			litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
		end
	end
	if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
		litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid;
		litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first;
		litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last;
		litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
		litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
	end
	if (litedramcore_bankmachine1_twtpcon_valid) begin
		litedramcore_bankmachine1_twtpcon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
			litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
			if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
				litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine1_trccon_valid) begin
		litedramcore_bankmachine1_trccon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine1_trccon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine1_trccon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine1_trccon_ready)) begin
			litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
			if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
				litedramcore_bankmachine1_trccon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine1_trascon_valid) begin
		litedramcore_bankmachine1_trascon_count <= 3'd4;
		if (1'd0) begin
			litedramcore_bankmachine1_trascon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine1_trascon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine1_trascon_ready)) begin
			litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
			if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
				litedramcore_bankmachine1_trascon_ready <= 1'd1;
			end
		end
	end
	bankmachine1_state <= bankmachine1_next_state;
	if (litedramcore_bankmachine2_row_close) begin
		litedramcore_bankmachine2_row_opened <= 1'd0;
	end else begin
		if (litedramcore_bankmachine2_row_open) begin
			litedramcore_bankmachine2_row_opened <= 1'd1;
			litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7];
		end
	end
	if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
		litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
	end
	if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
		litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
	end
	if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
		if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
			litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
		end
	end else begin
		if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
			litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
		end
	end
	if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
		litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid;
		litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first;
		litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last;
		litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
		litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
	end
	if (litedramcore_bankmachine2_twtpcon_valid) begin
		litedramcore_bankmachine2_twtpcon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
			litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
			if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
				litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine2_trccon_valid) begin
		litedramcore_bankmachine2_trccon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine2_trccon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine2_trccon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine2_trccon_ready)) begin
			litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
			if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
				litedramcore_bankmachine2_trccon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine2_trascon_valid) begin
		litedramcore_bankmachine2_trascon_count <= 3'd4;
		if (1'd0) begin
			litedramcore_bankmachine2_trascon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine2_trascon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine2_trascon_ready)) begin
			litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
			if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
				litedramcore_bankmachine2_trascon_ready <= 1'd1;
			end
		end
	end
	bankmachine2_state <= bankmachine2_next_state;
	if (litedramcore_bankmachine3_row_close) begin
		litedramcore_bankmachine3_row_opened <= 1'd0;
	end else begin
		if (litedramcore_bankmachine3_row_open) begin
			litedramcore_bankmachine3_row_opened <= 1'd1;
			litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7];
		end
	end
	if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
		litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
	end
	if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
		litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
	end
	if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
		if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
			litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
		end
	end else begin
		if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
			litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
		end
	end
	if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
		litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid;
		litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first;
		litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last;
		litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
		litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
	end
	if (litedramcore_bankmachine3_twtpcon_valid) begin
		litedramcore_bankmachine3_twtpcon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
			litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
			if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
				litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine3_trccon_valid) begin
		litedramcore_bankmachine3_trccon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine3_trccon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine3_trccon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine3_trccon_ready)) begin
			litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
			if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
				litedramcore_bankmachine3_trccon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine3_trascon_valid) begin
		litedramcore_bankmachine3_trascon_count <= 3'd4;
		if (1'd0) begin
			litedramcore_bankmachine3_trascon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine3_trascon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine3_trascon_ready)) begin
			litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
			if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
				litedramcore_bankmachine3_trascon_ready <= 1'd1;
			end
		end
	end
	bankmachine3_state <= bankmachine3_next_state;
	if (litedramcore_bankmachine4_row_close) begin
		litedramcore_bankmachine4_row_opened <= 1'd0;
	end else begin
		if (litedramcore_bankmachine4_row_open) begin
			litedramcore_bankmachine4_row_opened <= 1'd1;
			litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7];
		end
	end
	if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
		litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
	end
	if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
		litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
	end
	if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
		if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
			litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
		end
	end else begin
		if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
			litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
		end
	end
	if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
		litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid;
		litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first;
		litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last;
		litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
		litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
	end
	if (litedramcore_bankmachine4_twtpcon_valid) begin
		litedramcore_bankmachine4_twtpcon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
			litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
			if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
				litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine4_trccon_valid) begin
		litedramcore_bankmachine4_trccon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine4_trccon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine4_trccon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine4_trccon_ready)) begin
			litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
			if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
				litedramcore_bankmachine4_trccon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine4_trascon_valid) begin
		litedramcore_bankmachine4_trascon_count <= 3'd4;
		if (1'd0) begin
			litedramcore_bankmachine4_trascon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine4_trascon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine4_trascon_ready)) begin
			litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
			if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
				litedramcore_bankmachine4_trascon_ready <= 1'd1;
			end
		end
	end
	bankmachine4_state <= bankmachine4_next_state;
	if (litedramcore_bankmachine5_row_close) begin
		litedramcore_bankmachine5_row_opened <= 1'd0;
	end else begin
		if (litedramcore_bankmachine5_row_open) begin
			litedramcore_bankmachine5_row_opened <= 1'd1;
			litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7];
		end
	end
	if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
		litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
	end
	if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
		litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
	end
	if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
		if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
			litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
		end
	end else begin
		if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
			litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
		end
	end
	if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
		litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid;
		litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first;
		litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last;
		litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
		litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
	end
	if (litedramcore_bankmachine5_twtpcon_valid) begin
		litedramcore_bankmachine5_twtpcon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
			litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
			if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
				litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine5_trccon_valid) begin
		litedramcore_bankmachine5_trccon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine5_trccon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine5_trccon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine5_trccon_ready)) begin
			litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
			if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
				litedramcore_bankmachine5_trccon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine5_trascon_valid) begin
		litedramcore_bankmachine5_trascon_count <= 3'd4;
		if (1'd0) begin
			litedramcore_bankmachine5_trascon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine5_trascon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine5_trascon_ready)) begin
			litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
			if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
				litedramcore_bankmachine5_trascon_ready <= 1'd1;
			end
		end
	end
	bankmachine5_state <= bankmachine5_next_state;
	if (litedramcore_bankmachine6_row_close) begin
		litedramcore_bankmachine6_row_opened <= 1'd0;
	end else begin
		if (litedramcore_bankmachine6_row_open) begin
			litedramcore_bankmachine6_row_opened <= 1'd1;
			litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7];
		end
	end
	if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
		litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
	end
	if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
		litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
	end
	if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
		if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
			litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
		end
	end else begin
		if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
			litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
		end
	end
	if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
		litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid;
		litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first;
		litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last;
		litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
		litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
	end
	if (litedramcore_bankmachine6_twtpcon_valid) begin
		litedramcore_bankmachine6_twtpcon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
			litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
			if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
				litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine6_trccon_valid) begin
		litedramcore_bankmachine6_trccon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine6_trccon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine6_trccon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine6_trccon_ready)) begin
			litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
			if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
				litedramcore_bankmachine6_trccon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine6_trascon_valid) begin
		litedramcore_bankmachine6_trascon_count <= 3'd4;
		if (1'd0) begin
			litedramcore_bankmachine6_trascon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine6_trascon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine6_trascon_ready)) begin
			litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
			if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
				litedramcore_bankmachine6_trascon_ready <= 1'd1;
			end
		end
	end
	bankmachine6_state <= bankmachine6_next_state;
	if (litedramcore_bankmachine7_row_close) begin
		litedramcore_bankmachine7_row_opened <= 1'd0;
	end else begin
		if (litedramcore_bankmachine7_row_open) begin
			litedramcore_bankmachine7_row_opened <= 1'd1;
			litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7];
		end
	end
	if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
		litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
	end
	if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
		litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
	end
	if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
		if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
			litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
		end
	end else begin
		if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
			litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
		end
	end
	if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
		litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid;
		litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first;
		litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last;
		litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
		litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
	end
	if (litedramcore_bankmachine7_twtpcon_valid) begin
		litedramcore_bankmachine7_twtpcon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
			litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
			if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
				litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine7_trccon_valid) begin
		litedramcore_bankmachine7_trccon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine7_trccon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine7_trccon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine7_trccon_ready)) begin
			litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
			if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
				litedramcore_bankmachine7_trccon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine7_trascon_valid) begin
		litedramcore_bankmachine7_trascon_count <= 3'd4;
		if (1'd0) begin
			litedramcore_bankmachine7_trascon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine7_trascon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine7_trascon_ready)) begin
			litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
			if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
				litedramcore_bankmachine7_trascon_ready <= 1'd1;
			end
		end
	end
	bankmachine7_state <= bankmachine7_next_state;
	if ((~litedramcore_en0)) begin
		litedramcore_time0 <= 5'd31;
	end else begin
		if ((~litedramcore_max_time0)) begin
			litedramcore_time0 <= (litedramcore_time0 - 1'd1);
		end
	end
	if ((~litedramcore_en1)) begin
		litedramcore_time1 <= 4'd15;
	end else begin
		if ((~litedramcore_max_time1)) begin
			litedramcore_time1 <= (litedramcore_time1 - 1'd1);
		end
	end
	if (litedramcore_choose_cmd_ce) begin
		case (litedramcore_choose_cmd_grant)
			1'd0: begin
				if (litedramcore_choose_cmd_request[1]) begin
					litedramcore_choose_cmd_grant <= 1'd1;
				end else begin
					if (litedramcore_choose_cmd_request[2]) begin
						litedramcore_choose_cmd_grant <= 2'd2;
					end else begin
						if (litedramcore_choose_cmd_request[3]) begin
							litedramcore_choose_cmd_grant <= 2'd3;
						end else begin
							if (litedramcore_choose_cmd_request[4]) begin
								litedramcore_choose_cmd_grant <= 3'd4;
							end else begin
								if (litedramcore_choose_cmd_request[5]) begin
									litedramcore_choose_cmd_grant <= 3'd5;
								end else begin
									if (litedramcore_choose_cmd_request[6]) begin
										litedramcore_choose_cmd_grant <= 3'd6;
									end else begin
										if (litedramcore_choose_cmd_request[7]) begin
											litedramcore_choose_cmd_grant <= 3'd7;
										end
									end
								end
							end
						end
					end
				end
			end
			1'd1: begin
				if (litedramcore_choose_cmd_request[2]) begin
					litedramcore_choose_cmd_grant <= 2'd2;
				end else begin
					if (litedramcore_choose_cmd_request[3]) begin
						litedramcore_choose_cmd_grant <= 2'd3;
					end else begin
						if (litedramcore_choose_cmd_request[4]) begin
							litedramcore_choose_cmd_grant <= 3'd4;
						end else begin
							if (litedramcore_choose_cmd_request[5]) begin
								litedramcore_choose_cmd_grant <= 3'd5;
							end else begin
								if (litedramcore_choose_cmd_request[6]) begin
									litedramcore_choose_cmd_grant <= 3'd6;
								end else begin
									if (litedramcore_choose_cmd_request[7]) begin
										litedramcore_choose_cmd_grant <= 3'd7;
									end else begin
										if (litedramcore_choose_cmd_request[0]) begin
											litedramcore_choose_cmd_grant <= 1'd0;
										end
									end
								end
							end
						end
					end
				end
			end
			2'd2: begin
				if (litedramcore_choose_cmd_request[3]) begin
					litedramcore_choose_cmd_grant <= 2'd3;
				end else begin
					if (litedramcore_choose_cmd_request[4]) begin
						litedramcore_choose_cmd_grant <= 3'd4;
					end else begin
						if (litedramcore_choose_cmd_request[5]) begin
							litedramcore_choose_cmd_grant <= 3'd5;
						end else begin
							if (litedramcore_choose_cmd_request[6]) begin
								litedramcore_choose_cmd_grant <= 3'd6;
							end else begin
								if (litedramcore_choose_cmd_request[7]) begin
									litedramcore_choose_cmd_grant <= 3'd7;
								end else begin
									if (litedramcore_choose_cmd_request[0]) begin
										litedramcore_choose_cmd_grant <= 1'd0;
									end else begin
										if (litedramcore_choose_cmd_request[1]) begin
											litedramcore_choose_cmd_grant <= 1'd1;
										end
									end
								end
							end
						end
					end
				end
			end
			2'd3: begin
				if (litedramcore_choose_cmd_request[4]) begin
					litedramcore_choose_cmd_grant <= 3'd4;
				end else begin
					if (litedramcore_choose_cmd_request[5]) begin
						litedramcore_choose_cmd_grant <= 3'd5;
					end else begin
						if (litedramcore_choose_cmd_request[6]) begin
							litedramcore_choose_cmd_grant <= 3'd6;
						end else begin
							if (litedramcore_choose_cmd_request[7]) begin
								litedramcore_choose_cmd_grant <= 3'd7;
							end else begin
								if (litedramcore_choose_cmd_request[0]) begin
									litedramcore_choose_cmd_grant <= 1'd0;
								end else begin
									if (litedramcore_choose_cmd_request[1]) begin
										litedramcore_choose_cmd_grant <= 1'd1;
									end else begin
										if (litedramcore_choose_cmd_request[2]) begin
											litedramcore_choose_cmd_grant <= 2'd2;
										end
									end
								end
							end
						end
					end
				end
			end
			3'd4: begin
				if (litedramcore_choose_cmd_request[5]) begin
					litedramcore_choose_cmd_grant <= 3'd5;
				end else begin
					if (litedramcore_choose_cmd_request[6]) begin
						litedramcore_choose_cmd_grant <= 3'd6;
					end else begin
						if (litedramcore_choose_cmd_request[7]) begin
							litedramcore_choose_cmd_grant <= 3'd7;
						end else begin
							if (litedramcore_choose_cmd_request[0]) begin
								litedramcore_choose_cmd_grant <= 1'd0;
							end else begin
								if (litedramcore_choose_cmd_request[1]) begin
									litedramcore_choose_cmd_grant <= 1'd1;
								end else begin
									if (litedramcore_choose_cmd_request[2]) begin
										litedramcore_choose_cmd_grant <= 2'd2;
									end else begin
										if (litedramcore_choose_cmd_request[3]) begin
											litedramcore_choose_cmd_grant <= 2'd3;
										end
									end
								end
							end
						end
					end
				end
			end
			3'd5: begin
				if (litedramcore_choose_cmd_request[6]) begin
					litedramcore_choose_cmd_grant <= 3'd6;
				end else begin
					if (litedramcore_choose_cmd_request[7]) begin
						litedramcore_choose_cmd_grant <= 3'd7;
					end else begin
						if (litedramcore_choose_cmd_request[0]) begin
							litedramcore_choose_cmd_grant <= 1'd0;
						end else begin
							if (litedramcore_choose_cmd_request[1]) begin
								litedramcore_choose_cmd_grant <= 1'd1;
							end else begin
								if (litedramcore_choose_cmd_request[2]) begin
									litedramcore_choose_cmd_grant <= 2'd2;
								end else begin
									if (litedramcore_choose_cmd_request[3]) begin
										litedramcore_choose_cmd_grant <= 2'd3;
									end else begin
										if (litedramcore_choose_cmd_request[4]) begin
											litedramcore_choose_cmd_grant <= 3'd4;
										end
									end
								end
							end
						end
					end
				end
			end
			3'd6: begin
				if (litedramcore_choose_cmd_request[7]) begin
					litedramcore_choose_cmd_grant <= 3'd7;
				end else begin
					if (litedramcore_choose_cmd_request[0]) begin
						litedramcore_choose_cmd_grant <= 1'd0;
					end else begin
						if (litedramcore_choose_cmd_request[1]) begin
							litedramcore_choose_cmd_grant <= 1'd1;
						end else begin
							if (litedramcore_choose_cmd_request[2]) begin
								litedramcore_choose_cmd_grant <= 2'd2;
							end else begin
								if (litedramcore_choose_cmd_request[3]) begin
									litedramcore_choose_cmd_grant <= 2'd3;
								end else begin
									if (litedramcore_choose_cmd_request[4]) begin
										litedramcore_choose_cmd_grant <= 3'd4;
									end else begin
										if (litedramcore_choose_cmd_request[5]) begin
											litedramcore_choose_cmd_grant <= 3'd5;
										end
									end
								end
							end
						end
					end
				end
			end
			3'd7: begin
				if (litedramcore_choose_cmd_request[0]) begin
					litedramcore_choose_cmd_grant <= 1'd0;
				end else begin
					if (litedramcore_choose_cmd_request[1]) begin
						litedramcore_choose_cmd_grant <= 1'd1;
					end else begin
						if (litedramcore_choose_cmd_request[2]) begin
							litedramcore_choose_cmd_grant <= 2'd2;
						end else begin
							if (litedramcore_choose_cmd_request[3]) begin
								litedramcore_choose_cmd_grant <= 2'd3;
							end else begin
								if (litedramcore_choose_cmd_request[4]) begin
									litedramcore_choose_cmd_grant <= 3'd4;
								end else begin
									if (litedramcore_choose_cmd_request[5]) begin
										litedramcore_choose_cmd_grant <= 3'd5;
									end else begin
										if (litedramcore_choose_cmd_request[6]) begin
											litedramcore_choose_cmd_grant <= 3'd6;
										end
									end
								end
							end
						end
					end
				end
			end
		endcase
	end
	if (litedramcore_choose_req_ce) begin
		case (litedramcore_choose_req_grant)
			1'd0: begin
				if (litedramcore_choose_req_request[1]) begin
					litedramcore_choose_req_grant <= 1'd1;
				end else begin
					if (litedramcore_choose_req_request[2]) begin
						litedramcore_choose_req_grant <= 2'd2;
					end else begin
						if (litedramcore_choose_req_request[3]) begin
							litedramcore_choose_req_grant <= 2'd3;
						end else begin
							if (litedramcore_choose_req_request[4]) begin
								litedramcore_choose_req_grant <= 3'd4;
							end else begin
								if (litedramcore_choose_req_request[5]) begin
									litedramcore_choose_req_grant <= 3'd5;
								end else begin
									if (litedramcore_choose_req_request[6]) begin
										litedramcore_choose_req_grant <= 3'd6;
									end else begin
										if (litedramcore_choose_req_request[7]) begin
											litedramcore_choose_req_grant <= 3'd7;
										end
									end
								end
							end
						end
					end
				end
			end
			1'd1: begin
				if (litedramcore_choose_req_request[2]) begin
					litedramcore_choose_req_grant <= 2'd2;
				end else begin
					if (litedramcore_choose_req_request[3]) begin
						litedramcore_choose_req_grant <= 2'd3;
					end else begin
						if (litedramcore_choose_req_request[4]) begin
							litedramcore_choose_req_grant <= 3'd4;
						end else begin
							if (litedramcore_choose_req_request[5]) begin
								litedramcore_choose_req_grant <= 3'd5;
							end else begin
								if (litedramcore_choose_req_request[6]) begin
									litedramcore_choose_req_grant <= 3'd6;
								end else begin
									if (litedramcore_choose_req_request[7]) begin
										litedramcore_choose_req_grant <= 3'd7;
									end else begin
										if (litedramcore_choose_req_request[0]) begin
											litedramcore_choose_req_grant <= 1'd0;
										end
									end
								end
							end
						end
					end
				end
			end
			2'd2: begin
				if (litedramcore_choose_req_request[3]) begin
					litedramcore_choose_req_grant <= 2'd3;
				end else begin
					if (litedramcore_choose_req_request[4]) begin
						litedramcore_choose_req_grant <= 3'd4;
					end else begin
						if (litedramcore_choose_req_request[5]) begin
							litedramcore_choose_req_grant <= 3'd5;
						end else begin
							if (litedramcore_choose_req_request[6]) begin
								litedramcore_choose_req_grant <= 3'd6;
							end else begin
								if (litedramcore_choose_req_request[7]) begin
									litedramcore_choose_req_grant <= 3'd7;
								end else begin
									if (litedramcore_choose_req_request[0]) begin
										litedramcore_choose_req_grant <= 1'd0;
									end else begin
										if (litedramcore_choose_req_request[1]) begin
											litedramcore_choose_req_grant <= 1'd1;
										end
									end
								end
							end
						end
					end
				end
			end
			2'd3: begin
				if (litedramcore_choose_req_request[4]) begin
					litedramcore_choose_req_grant <= 3'd4;
				end else begin
					if (litedramcore_choose_req_request[5]) begin
						litedramcore_choose_req_grant <= 3'd5;
					end else begin
						if (litedramcore_choose_req_request[6]) begin
							litedramcore_choose_req_grant <= 3'd6;
						end else begin
							if (litedramcore_choose_req_request[7]) begin
								litedramcore_choose_req_grant <= 3'd7;
							end else begin
								if (litedramcore_choose_req_request[0]) begin
									litedramcore_choose_req_grant <= 1'd0;
								end else begin
									if (litedramcore_choose_req_request[1]) begin
										litedramcore_choose_req_grant <= 1'd1;
									end else begin
										if (litedramcore_choose_req_request[2]) begin
											litedramcore_choose_req_grant <= 2'd2;
										end
									end
								end
							end
						end
					end
				end
			end
			3'd4: begin
				if (litedramcore_choose_req_request[5]) begin
					litedramcore_choose_req_grant <= 3'd5;
				end else begin
					if (litedramcore_choose_req_request[6]) begin
						litedramcore_choose_req_grant <= 3'd6;
					end else begin
						if (litedramcore_choose_req_request[7]) begin
							litedramcore_choose_req_grant <= 3'd7;
						end else begin
							if (litedramcore_choose_req_request[0]) begin
								litedramcore_choose_req_grant <= 1'd0;
							end else begin
								if (litedramcore_choose_req_request[1]) begin
									litedramcore_choose_req_grant <= 1'd1;
								end else begin
									if (litedramcore_choose_req_request[2]) begin
										litedramcore_choose_req_grant <= 2'd2;
									end else begin
										if (litedramcore_choose_req_request[3]) begin
											litedramcore_choose_req_grant <= 2'd3;
										end
									end
								end
							end
						end
					end
				end
			end
			3'd5: begin
				if (litedramcore_choose_req_request[6]) begin
					litedramcore_choose_req_grant <= 3'd6;
				end else begin
					if (litedramcore_choose_req_request[7]) begin
						litedramcore_choose_req_grant <= 3'd7;
					end else begin
						if (litedramcore_choose_req_request[0]) begin
							litedramcore_choose_req_grant <= 1'd0;
						end else begin
							if (litedramcore_choose_req_request[1]) begin
								litedramcore_choose_req_grant <= 1'd1;
							end else begin
								if (litedramcore_choose_req_request[2]) begin
									litedramcore_choose_req_grant <= 2'd2;
								end else begin
									if (litedramcore_choose_req_request[3]) begin
										litedramcore_choose_req_grant <= 2'd3;
									end else begin
										if (litedramcore_choose_req_request[4]) begin
											litedramcore_choose_req_grant <= 3'd4;
										end
									end
								end
							end
						end
					end
				end
			end
			3'd6: begin
				if (litedramcore_choose_req_request[7]) begin
					litedramcore_choose_req_grant <= 3'd7;
				end else begin
					if (litedramcore_choose_req_request[0]) begin
						litedramcore_choose_req_grant <= 1'd0;
					end else begin
						if (litedramcore_choose_req_request[1]) begin
							litedramcore_choose_req_grant <= 1'd1;
						end else begin
							if (litedramcore_choose_req_request[2]) begin
								litedramcore_choose_req_grant <= 2'd2;
							end else begin
								if (litedramcore_choose_req_request[3]) begin
									litedramcore_choose_req_grant <= 2'd3;
								end else begin
									if (litedramcore_choose_req_request[4]) begin
										litedramcore_choose_req_grant <= 3'd4;
									end else begin
										if (litedramcore_choose_req_request[5]) begin
											litedramcore_choose_req_grant <= 3'd5;
										end
									end
								end
							end
						end
					end
				end
			end
			3'd7: begin
				if (litedramcore_choose_req_request[0]) begin
					litedramcore_choose_req_grant <= 1'd0;
				end else begin
					if (litedramcore_choose_req_request[1]) begin
						litedramcore_choose_req_grant <= 1'd1;
					end else begin
						if (litedramcore_choose_req_request[2]) begin
							litedramcore_choose_req_grant <= 2'd2;
						end else begin
							if (litedramcore_choose_req_request[3]) begin
								litedramcore_choose_req_grant <= 2'd3;
							end else begin
								if (litedramcore_choose_req_request[4]) begin
									litedramcore_choose_req_grant <= 3'd4;
								end else begin
									if (litedramcore_choose_req_request[5]) begin
										litedramcore_choose_req_grant <= 3'd5;
									end else begin
										if (litedramcore_choose_req_request[6]) begin
											litedramcore_choose_req_grant <= 3'd6;
										end
									end
								end
							end
						end
					end
				end
			end
		endcase
	end
	litedramcore_dfi_p0_cs_n <= 1'd0;
	litedramcore_dfi_p0_bank <= array_muxed0;
	litedramcore_dfi_p0_address <= array_muxed1;
	litedramcore_dfi_p0_cas_n <= (~array_muxed2);
	litedramcore_dfi_p0_ras_n <= (~array_muxed3);
	litedramcore_dfi_p0_we_n <= (~array_muxed4);
	litedramcore_dfi_p0_rddata_en <= array_muxed5;
	litedramcore_dfi_p0_wrdata_en <= array_muxed6;
	litedramcore_dfi_p1_cs_n <= 1'd0;
	litedramcore_dfi_p1_bank <= array_muxed7;
	litedramcore_dfi_p1_address <= array_muxed8;
	litedramcore_dfi_p1_cas_n <= (~array_muxed9);
	litedramcore_dfi_p1_ras_n <= (~array_muxed10);
	litedramcore_dfi_p1_we_n <= (~array_muxed11);
	litedramcore_dfi_p1_rddata_en <= array_muxed12;
	litedramcore_dfi_p1_wrdata_en <= array_muxed13;
	litedramcore_dfi_p2_cs_n <= 1'd0;
	litedramcore_dfi_p2_bank <= array_muxed14;
	litedramcore_dfi_p2_address <= array_muxed15;
	litedramcore_dfi_p2_cas_n <= (~array_muxed16);
	litedramcore_dfi_p2_ras_n <= (~array_muxed17);
	litedramcore_dfi_p2_we_n <= (~array_muxed18);
	litedramcore_dfi_p2_rddata_en <= array_muxed19;
	litedramcore_dfi_p2_wrdata_en <= array_muxed20;
	litedramcore_dfi_p3_cs_n <= 1'd0;
	litedramcore_dfi_p3_bank <= array_muxed21;
	litedramcore_dfi_p3_address <= array_muxed22;
	litedramcore_dfi_p3_cas_n <= (~array_muxed23);
	litedramcore_dfi_p3_ras_n <= (~array_muxed24);
	litedramcore_dfi_p3_we_n <= (~array_muxed25);
	litedramcore_dfi_p3_rddata_en <= array_muxed26;
	litedramcore_dfi_p3_wrdata_en <= array_muxed27;
	if (litedramcore_trrdcon_valid) begin
		litedramcore_trrdcon_count <= 1'd1;
		if (1'd0) begin
			litedramcore_trrdcon_ready <= 1'd1;
		end else begin
			litedramcore_trrdcon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_trrdcon_ready)) begin
			litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
			if ((litedramcore_trrdcon_count == 1'd1)) begin
				litedramcore_trrdcon_ready <= 1'd1;
			end
		end
	end
	litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
	if ((litedramcore_tfawcon_count < 3'd4)) begin
		if ((litedramcore_tfawcon_count == 2'd3)) begin
			litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
		end else begin
			litedramcore_tfawcon_ready <= 1'd1;
		end
	end
	if (litedramcore_tccdcon_valid) begin
		litedramcore_tccdcon_count <= 1'd0;
		if (1'd1) begin
			litedramcore_tccdcon_ready <= 1'd1;
		end else begin
			litedramcore_tccdcon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_tccdcon_ready)) begin
			litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
			if ((litedramcore_tccdcon_count == 1'd1)) begin
				litedramcore_tccdcon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_twtrcon_valid) begin
		litedramcore_twtrcon_count <= 3'd4;
		if (1'd0) begin
			litedramcore_twtrcon_ready <= 1'd1;
		end else begin
			litedramcore_twtrcon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_twtrcon_ready)) begin
			litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
			if ((litedramcore_twtrcon_count == 1'd1)) begin
				litedramcore_twtrcon_ready <= 1'd1;
			end
		end
	end
	multiplexer_state <= multiplexer_next_state;
	new_master_wdata_ready0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
	new_master_wdata_ready1 <= new_master_wdata_ready0;
	new_master_wdata_ready2 <= new_master_wdata_ready1;
	new_master_rdata_valid0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
	new_master_rdata_valid1 <= new_master_rdata_valid0;
	new_master_rdata_valid2 <= new_master_rdata_valid1;
	new_master_rdata_valid3 <= new_master_rdata_valid2;
	new_master_rdata_valid4 <= new_master_rdata_valid3;
	new_master_rdata_valid5 <= new_master_rdata_valid4;
	new_master_rdata_valid6 <= new_master_rdata_valid5;
	new_master_rdata_valid7 <= new_master_rdata_valid6;
	new_master_rdata_valid8 <= new_master_rdata_valid7;
	interface0_bank_bus_dat_r <= 1'd0;
	if (csrbank0_sel) begin
		case (interface0_bank_bus_adr[1])
			1'd0: begin
				interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
			end
			1'd1: begin
				interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
			end
		endcase
	end
	if (csrbank0_init_done0_re) begin
		init_done_storage <= csrbank0_init_done0_r;
	end
	init_done_re <= csrbank0_init_done0_re;
	if (csrbank0_init_error0_re) begin
		init_error_storage <= csrbank0_init_error0_r;
	end
	init_error_re <= csrbank0_init_error0_re;
	interface1_bank_bus_dat_r <= 1'd0;
	if (csrbank1_sel) begin
		case (interface1_bank_bus_adr[4:1])
			1'd0: begin
				interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
			end
			1'd1: begin
				interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w;
			end
			2'd2: begin
				interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w;
			end
			2'd3: begin
				interface1_bank_bus_dat_r <= a7ddrphy_cdly_rst_w;
			end
			3'd4: begin
				interface1_bank_bus_dat_r <= a7ddrphy_cdly_inc_w;
			end
			3'd5: begin
				interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
			end
			3'd6: begin
				interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w;
			end
			3'd7: begin
				interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w;
			end
			4'd8: begin
				interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w;
			end
			4'd9: begin
				interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w;
			end
		endcase
	end
	if (csrbank1_half_sys8x_taps0_re) begin
		a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r;
	end
	a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re;
	if (csrbank1_wlevel_en0_re) begin
		a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r;
	end
	a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re;
	if (csrbank1_dly_sel0_re) begin
		a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r;
	end
	a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
	interface2_bank_bus_dat_r <= 1'd0;
	if (csrbank2_sel) begin
		case (interface2_bank_bus_adr[5:1])
			1'd0: begin
				interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
			end
			1'd1: begin
				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
			end
			2'd2: begin
				interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
			end
			2'd3: begin
				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
			end
			3'd4: begin
				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
			end
			3'd5: begin
				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
			end
			3'd6: begin
				interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w;
			end
			3'd7: begin
				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
			end
			4'd8: begin
				interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
			end
			4'd9: begin
				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
			end
			4'd10: begin
				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
			end
			4'd11: begin
				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
			end
			4'd12: begin
				interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w;
			end
			4'd13: begin
				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
			end
			4'd14: begin
				interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
			end
			4'd15: begin
				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
			end
			5'd16: begin
				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
			end
			5'd17: begin
				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
			end
			5'd18: begin
				interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w;
			end
			5'd19: begin
				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
			end
			5'd20: begin
				interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
			end
			5'd21: begin
				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
			end
			5'd22: begin
				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
			end
			5'd23: begin
				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
			end
			5'd24: begin
				interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w;
			end
		endcase
	end
	if (csrbank2_dfii_control0_re) begin
		litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
	end
	litedramcore_re <= csrbank2_dfii_control0_re;
	if (csrbank2_dfii_pi0_command0_re) begin
		litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
	end
	litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
	if (csrbank2_dfii_pi0_address0_re) begin
		litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r;
	end
	litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
	if (csrbank2_dfii_pi0_baddress0_re) begin
		litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
	end
	litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
	if (csrbank2_dfii_pi0_wrdata0_re) begin
		litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
	end
	litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
	if (csrbank2_dfii_pi1_command0_re) begin
		litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
	end
	litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
	if (csrbank2_dfii_pi1_address0_re) begin
		litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r;
	end
	litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
	if (csrbank2_dfii_pi1_baddress0_re) begin
		litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
	end
	litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
	if (csrbank2_dfii_pi1_wrdata0_re) begin
		litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
	end
	litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
	if (csrbank2_dfii_pi2_command0_re) begin
		litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
	end
	litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
	if (csrbank2_dfii_pi2_address0_re) begin
		litedramcore_phaseinjector2_address_storage[14:0] <= csrbank2_dfii_pi2_address0_r;
	end
	litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
	if (csrbank2_dfii_pi2_baddress0_re) begin
		litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
	end
	litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
	if (csrbank2_dfii_pi2_wrdata0_re) begin
		litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r;
	end
	litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
	if (csrbank2_dfii_pi3_command0_re) begin
		litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
	end
	litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
	if (csrbank2_dfii_pi3_address0_re) begin
		litedramcore_phaseinjector3_address_storage[14:0] <= csrbank2_dfii_pi3_address0_r;
	end
	litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
	if (csrbank2_dfii_pi3_baddress0_re) begin
		litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
	end
	litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
	if (csrbank2_dfii_pi3_wrdata0_re) begin
		litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r;
	end
	litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
	if (sys_rst) begin
		a7ddrphy_half_sys8x_taps_storage <= 5'd8;
		a7ddrphy_half_sys8x_taps_re <= 1'd0;
		a7ddrphy_wlevel_en_storage <= 1'd0;
		a7ddrphy_wlevel_en_re <= 1'd0;
		a7ddrphy_dly_sel_storage <= 2'd0;
		a7ddrphy_dly_sel_re <= 1'd0;
		a7ddrphy_dfi_p0_rddata_valid <= 1'd0;
		a7ddrphy_dfi_p1_rddata_valid <= 1'd0;
		a7ddrphy_dfi_p2_rddata_valid <= 1'd0;
		a7ddrphy_dfi_p3_rddata_valid <= 1'd0;
		a7ddrphy_dqs_oe_delayed <= 1'd0;
		a7ddrphy_dqspattern_o1 <= 8'd0;
		a7ddrphy_dq_oe_delayed <= 1'd0;
		a7ddrphy_bitslip0_value <= 4'd0;
		a7ddrphy_bitslip1_value <= 4'd0;
		a7ddrphy_bitslip2_value <= 4'd0;
		a7ddrphy_bitslip3_value <= 4'd0;
		a7ddrphy_bitslip4_value <= 4'd0;
		a7ddrphy_bitslip5_value <= 4'd0;
		a7ddrphy_bitslip6_value <= 4'd0;
		a7ddrphy_bitslip7_value <= 4'd0;
		a7ddrphy_bitslip8_value <= 4'd0;
		a7ddrphy_bitslip9_value <= 4'd0;
		a7ddrphy_bitslip10_value <= 4'd0;
		a7ddrphy_bitslip11_value <= 4'd0;
		a7ddrphy_bitslip12_value <= 4'd0;
		a7ddrphy_bitslip13_value <= 4'd0;
		a7ddrphy_bitslip14_value <= 4'd0;
		a7ddrphy_bitslip15_value <= 4'd0;
		a7ddrphy_rddata_en_last <= 8'd0;
		a7ddrphy_wrdata_en_last <= 4'd0;
		litedramcore_storage <= 4'd0;
		litedramcore_re <= 1'd0;
		litedramcore_phaseinjector0_command_storage <= 6'd0;
		litedramcore_phaseinjector0_command_re <= 1'd0;
		litedramcore_phaseinjector0_address_re <= 1'd0;
		litedramcore_phaseinjector0_baddress_re <= 1'd0;
		litedramcore_phaseinjector0_wrdata_re <= 1'd0;
		litedramcore_phaseinjector0_status <= 32'd0;
		litedramcore_phaseinjector1_command_storage <= 6'd0;
		litedramcore_phaseinjector1_command_re <= 1'd0;
		litedramcore_phaseinjector1_address_re <= 1'd0;
		litedramcore_phaseinjector1_baddress_re <= 1'd0;
		litedramcore_phaseinjector1_wrdata_re <= 1'd0;
		litedramcore_phaseinjector1_status <= 32'd0;
		litedramcore_phaseinjector2_command_storage <= 6'd0;
		litedramcore_phaseinjector2_command_re <= 1'd0;
		litedramcore_phaseinjector2_address_re <= 1'd0;
		litedramcore_phaseinjector2_baddress_re <= 1'd0;
		litedramcore_phaseinjector2_wrdata_re <= 1'd0;
		litedramcore_phaseinjector2_status <= 32'd0;
		litedramcore_phaseinjector3_command_storage <= 6'd0;
		litedramcore_phaseinjector3_command_re <= 1'd0;
		litedramcore_phaseinjector3_address_re <= 1'd0;
		litedramcore_phaseinjector3_baddress_re <= 1'd0;
		litedramcore_phaseinjector3_wrdata_re <= 1'd0;
		litedramcore_phaseinjector3_status <= 32'd0;
		litedramcore_dfi_p0_address <= 15'd0;
		litedramcore_dfi_p0_bank <= 3'd0;
		litedramcore_dfi_p0_cas_n <= 1'd1;
		litedramcore_dfi_p0_cs_n <= 1'd1;
		litedramcore_dfi_p0_ras_n <= 1'd1;
		litedramcore_dfi_p0_we_n <= 1'd1;
		litedramcore_dfi_p0_wrdata_en <= 1'd0;
		litedramcore_dfi_p0_rddata_en <= 1'd0;
		litedramcore_dfi_p1_address <= 15'd0;
		litedramcore_dfi_p1_bank <= 3'd0;
		litedramcore_dfi_p1_cas_n <= 1'd1;
		litedramcore_dfi_p1_cs_n <= 1'd1;
		litedramcore_dfi_p1_ras_n <= 1'd1;
		litedramcore_dfi_p1_we_n <= 1'd1;
		litedramcore_dfi_p1_wrdata_en <= 1'd0;
		litedramcore_dfi_p1_rddata_en <= 1'd0;
		litedramcore_dfi_p2_address <= 15'd0;
		litedramcore_dfi_p2_bank <= 3'd0;
		litedramcore_dfi_p2_cas_n <= 1'd1;
		litedramcore_dfi_p2_cs_n <= 1'd1;
		litedramcore_dfi_p2_ras_n <= 1'd1;
		litedramcore_dfi_p2_we_n <= 1'd1;
		litedramcore_dfi_p2_wrdata_en <= 1'd0;
		litedramcore_dfi_p2_rddata_en <= 1'd0;
		litedramcore_dfi_p3_address <= 15'd0;
		litedramcore_dfi_p3_bank <= 3'd0;
		litedramcore_dfi_p3_cas_n <= 1'd1;
		litedramcore_dfi_p3_cs_n <= 1'd1;
		litedramcore_dfi_p3_ras_n <= 1'd1;
		litedramcore_dfi_p3_we_n <= 1'd1;
		litedramcore_dfi_p3_wrdata_en <= 1'd0;
		litedramcore_dfi_p3_rddata_en <= 1'd0;
		litedramcore_timer_count1 <= 10'd781;
		litedramcore_postponer_req_o <= 1'd0;
		litedramcore_postponer_count <= 1'd0;
		litedramcore_sequencer_done1 <= 1'd0;
		litedramcore_sequencer_counter <= 6'd0;
		litedramcore_sequencer_count <= 1'd0;
		litedramcore_zqcs_timer_count1 <= 27'd99999999;
		litedramcore_zqcs_executer_done <= 1'd0;
		litedramcore_zqcs_executer_counter <= 5'd0;
		litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
		litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
		litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
		litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
		litedramcore_bankmachine0_row <= 15'd0;
		litedramcore_bankmachine0_row_opened <= 1'd0;
		litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
		litedramcore_bankmachine0_twtpcon_count <= 3'd0;
		litedramcore_bankmachine0_trccon_ready <= 1'd0;
		litedramcore_bankmachine0_trccon_count <= 3'd0;
		litedramcore_bankmachine0_trascon_ready <= 1'd0;
		litedramcore_bankmachine0_trascon_count <= 3'd0;
		litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
		litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
		litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
		litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
		litedramcore_bankmachine1_row <= 15'd0;
		litedramcore_bankmachine1_row_opened <= 1'd0;
		litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
		litedramcore_bankmachine1_twtpcon_count <= 3'd0;
		litedramcore_bankmachine1_trccon_ready <= 1'd0;
		litedramcore_bankmachine1_trccon_count <= 3'd0;
		litedramcore_bankmachine1_trascon_ready <= 1'd0;
		litedramcore_bankmachine1_trascon_count <= 3'd0;
		litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
		litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
		litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
		litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
		litedramcore_bankmachine2_row <= 15'd0;
		litedramcore_bankmachine2_row_opened <= 1'd0;
		litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
		litedramcore_bankmachine2_twtpcon_count <= 3'd0;
		litedramcore_bankmachine2_trccon_ready <= 1'd0;
		litedramcore_bankmachine2_trccon_count <= 3'd0;
		litedramcore_bankmachine2_trascon_ready <= 1'd0;
		litedramcore_bankmachine2_trascon_count <= 3'd0;
		litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
		litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
		litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
		litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
		litedramcore_bankmachine3_row <= 15'd0;
		litedramcore_bankmachine3_row_opened <= 1'd0;
		litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
		litedramcore_bankmachine3_twtpcon_count <= 3'd0;
		litedramcore_bankmachine3_trccon_ready <= 1'd0;
		litedramcore_bankmachine3_trccon_count <= 3'd0;
		litedramcore_bankmachine3_trascon_ready <= 1'd0;
		litedramcore_bankmachine3_trascon_count <= 3'd0;
		litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
		litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
		litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
		litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
		litedramcore_bankmachine4_row <= 15'd0;
		litedramcore_bankmachine4_row_opened <= 1'd0;
		litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
		litedramcore_bankmachine4_twtpcon_count <= 3'd0;
		litedramcore_bankmachine4_trccon_ready <= 1'd0;
		litedramcore_bankmachine4_trccon_count <= 3'd0;
		litedramcore_bankmachine4_trascon_ready <= 1'd0;
		litedramcore_bankmachine4_trascon_count <= 3'd0;
		litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
		litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
		litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
		litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
		litedramcore_bankmachine5_row <= 15'd0;
		litedramcore_bankmachine5_row_opened <= 1'd0;
		litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
		litedramcore_bankmachine5_twtpcon_count <= 3'd0;
		litedramcore_bankmachine5_trccon_ready <= 1'd0;
		litedramcore_bankmachine5_trccon_count <= 3'd0;
		litedramcore_bankmachine5_trascon_ready <= 1'd0;
		litedramcore_bankmachine5_trascon_count <= 3'd0;
		litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
		litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
		litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
		litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
		litedramcore_bankmachine6_row <= 15'd0;
		litedramcore_bankmachine6_row_opened <= 1'd0;
		litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
		litedramcore_bankmachine6_twtpcon_count <= 3'd0;
		litedramcore_bankmachine6_trccon_ready <= 1'd0;
		litedramcore_bankmachine6_trccon_count <= 3'd0;
		litedramcore_bankmachine6_trascon_ready <= 1'd0;
		litedramcore_bankmachine6_trascon_count <= 3'd0;
		litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
		litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
		litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
		litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
		litedramcore_bankmachine7_row <= 15'd0;
		litedramcore_bankmachine7_row_opened <= 1'd0;
		litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
		litedramcore_bankmachine7_twtpcon_count <= 3'd0;
		litedramcore_bankmachine7_trccon_ready <= 1'd0;
		litedramcore_bankmachine7_trccon_count <= 3'd0;
		litedramcore_bankmachine7_trascon_ready <= 1'd0;
		litedramcore_bankmachine7_trascon_count <= 3'd0;
		litedramcore_choose_cmd_grant <= 3'd0;
		litedramcore_choose_req_grant <= 3'd0;
		litedramcore_trrdcon_ready <= 1'd0;
		litedramcore_trrdcon_count <= 1'd0;
		litedramcore_tfawcon_ready <= 1'd1;
		litedramcore_tfawcon_window <= 5'd0;
		litedramcore_tccdcon_ready <= 1'd0;
		litedramcore_tccdcon_count <= 1'd0;
		litedramcore_twtrcon_ready <= 1'd0;
		litedramcore_twtrcon_count <= 3'd0;
		litedramcore_time0 <= 5'd0;
		litedramcore_time1 <= 4'd0;
		init_done_storage <= 1'd0;
		init_done_re <= 1'd0;
		init_error_storage <= 1'd0;
		init_error_re <= 1'd0;
		state <= 1'd0;
		refresher_state <= 2'd0;
		bankmachine0_state <= 4'd0;
		bankmachine1_state <= 4'd0;
		bankmachine2_state <= 4'd0;
		bankmachine3_state <= 4'd0;
		bankmachine4_state <= 4'd0;
		bankmachine5_state <= 4'd0;
		bankmachine6_state <= 4'd0;
		bankmachine7_state <= 4'd0;
		multiplexer_state <= 4'd0;
		new_master_wdata_ready0 <= 1'd0;
		new_master_wdata_ready1 <= 1'd0;
		new_master_wdata_ready2 <= 1'd0;
		new_master_rdata_valid0 <= 1'd0;
		new_master_rdata_valid1 <= 1'd0;
		new_master_rdata_valid2 <= 1'd0;
		new_master_rdata_valid3 <= 1'd0;
		new_master_rdata_valid4 <= 1'd0;
		new_master_rdata_valid5 <= 1'd0;
		new_master_rdata_valid6 <= 1'd0;
		new_master_rdata_valid7 <= 1'd0;
		new_master_rdata_valid8 <= 1'd0;
	end
end

BUFG BUFG(
	.I(s7pll0_clkout0),
	.O(s7pll0_clkout_buf0)
);

BUFG BUFG_1(
	.I(s7pll0_clkout1),
	.O(s7pll0_clkout_buf1)
);

BUFG BUFG_2(
	.I(s7pll0_clkout2),
	.O(s7pll0_clkout_buf2)
);

BUFG BUFG_3(
	.I(s7pll1_clkout),
	.O(s7pll1_clkout_buf)
);

IDELAYCTRL IDELAYCTRL(
	.REFCLK(iodelay_clk),
	.RST(ic_reset)
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(1'd0),
	.D2(1'd1),
	.D3(1'd0),
	.D4(1'd1),
	.D5(1'd0),
	.D6(1'd1),
	.D7(1'd0),
	.D8(1'd1),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(a7ddrphy_sd_clk_se_nodelay)
);

OBUFDS OBUFDS(
	.I(a7ddrphy_sd_clk_se_nodelay),
	.O(ddram_clk_p),
	.OB(ddram_clk_n)
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_1 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_address[0]),
	.D2(a7ddrphy_dfi_p0_address[0]),
	.D3(a7ddrphy_dfi_p1_address[0]),
	.D4(a7ddrphy_dfi_p1_address[0]),
	.D5(a7ddrphy_dfi_p2_address[0]),
	.D6(a7ddrphy_dfi_p2_address[0]),
	.D7(a7ddrphy_dfi_p3_address[0]),
	.D8(a7ddrphy_dfi_p3_address[0]),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(ddram_a[0])
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_2 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_address[1]),
	.D2(a7ddrphy_dfi_p0_address[1]),
	.D3(a7ddrphy_dfi_p1_address[1]),
	.D4(a7ddrphy_dfi_p1_address[1]),
	.D5(a7ddrphy_dfi_p2_address[1]),
	.D6(a7ddrphy_dfi_p2_address[1]),
	.D7(a7ddrphy_dfi_p3_address[1]),
	.D8(a7ddrphy_dfi_p3_address[1]),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(ddram_a[1])
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_3 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_address[2]),
	.D2(a7ddrphy_dfi_p0_address[2]),
	.D3(a7ddrphy_dfi_p1_address[2]),
	.D4(a7ddrphy_dfi_p1_address[2]),
	.D5(a7ddrphy_dfi_p2_address[2]),
	.D6(a7ddrphy_dfi_p2_address[2]),
	.D7(a7ddrphy_dfi_p3_address[2]),
	.D8(a7ddrphy_dfi_p3_address[2]),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(ddram_a[2])
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_4 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_address[3]),
	.D2(a7ddrphy_dfi_p0_address[3]),
	.D3(a7ddrphy_dfi_p1_address[3]),
	.D4(a7ddrphy_dfi_p1_address[3]),
	.D5(a7ddrphy_dfi_p2_address[3]),
	.D6(a7ddrphy_dfi_p2_address[3]),
	.D7(a7ddrphy_dfi_p3_address[3]),
	.D8(a7ddrphy_dfi_p3_address[3]),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(ddram_a[3])
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_5 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_address[4]),
	.D2(a7ddrphy_dfi_p0_address[4]),
	.D3(a7ddrphy_dfi_p1_address[4]),
	.D4(a7ddrphy_dfi_p1_address[4]),
	.D5(a7ddrphy_dfi_p2_address[4]),
	.D6(a7ddrphy_dfi_p2_address[4]),
	.D7(a7ddrphy_dfi_p3_address[4]),
	.D8(a7ddrphy_dfi_p3_address[4]),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(ddram_a[4])
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_6 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_address[5]),
	.D2(a7ddrphy_dfi_p0_address[5]),
	.D3(a7ddrphy_dfi_p1_address[5]),
	.D4(a7ddrphy_dfi_p1_address[5]),
	.D5(a7ddrphy_dfi_p2_address[5]),
	.D6(a7ddrphy_dfi_p2_address[5]),
	.D7(a7ddrphy_dfi_p3_address[5]),
	.D8(a7ddrphy_dfi_p3_address[5]),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(ddram_a[5])
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_7 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_address[6]),
	.D2(a7ddrphy_dfi_p0_address[6]),
	.D3(a7ddrphy_dfi_p1_address[6]),
	.D4(a7ddrphy_dfi_p1_address[6]),
	.D5(a7ddrphy_dfi_p2_address[6]),
	.D6(a7ddrphy_dfi_p2_address[6]),
	.D7(a7ddrphy_dfi_p3_address[6]),
	.D8(a7ddrphy_dfi_p3_address[6]),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(ddram_a[6])
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_8 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_address[7]),
	.D2(a7ddrphy_dfi_p0_address[7]),
	.D3(a7ddrphy_dfi_p1_address[7]),
	.D4(a7ddrphy_dfi_p1_address[7]),
	.D5(a7ddrphy_dfi_p2_address[7]),
	.D6(a7ddrphy_dfi_p2_address[7]),
	.D7(a7ddrphy_dfi_p3_address[7]),
	.D8(a7ddrphy_dfi_p3_address[7]),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(ddram_a[7])
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_9 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_address[8]),
	.D2(a7ddrphy_dfi_p0_address[8]),
	.D3(a7ddrphy_dfi_p1_address[8]),
	.D4(a7ddrphy_dfi_p1_address[8]),
	.D5(a7ddrphy_dfi_p2_address[8]),
	.D6(a7ddrphy_dfi_p2_address[8]),
	.D7(a7ddrphy_dfi_p3_address[8]),
	.D8(a7ddrphy_dfi_p3_address[8]),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(ddram_a[8])
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_10 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_address[9]),
	.D2(a7ddrphy_dfi_p0_address[9]),
	.D3(a7ddrphy_dfi_p1_address[9]),
	.D4(a7ddrphy_dfi_p1_address[9]),
	.D5(a7ddrphy_dfi_p2_address[9]),
	.D6(a7ddrphy_dfi_p2_address[9]),
	.D7(a7ddrphy_dfi_p3_address[9]),
	.D8(a7ddrphy_dfi_p3_address[9]),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(ddram_a[9])
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_11 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_address[10]),
	.D2(a7ddrphy_dfi_p0_address[10]),
	.D3(a7ddrphy_dfi_p1_address[10]),
	.D4(a7ddrphy_dfi_p1_address[10]),
	.D5(a7ddrphy_dfi_p2_address[10]),
	.D6(a7ddrphy_dfi_p2_address[10]),
	.D7(a7ddrphy_dfi_p3_address[10]),
	.D8(a7ddrphy_dfi_p3_address[10]),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(ddram_a[10])
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_12 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_address[11]),
	.D2(a7ddrphy_dfi_p0_address[11]),
	.D3(a7ddrphy_dfi_p1_address[11]),
	.D4(a7ddrphy_dfi_p1_address[11]),
	.D5(a7ddrphy_dfi_p2_address[11]),
	.D6(a7ddrphy_dfi_p2_address[11]),
	.D7(a7ddrphy_dfi_p3_address[11]),
	.D8(a7ddrphy_dfi_p3_address[11]),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(ddram_a[11])
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_13 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_address[12]),
	.D2(a7ddrphy_dfi_p0_address[12]),
	.D3(a7ddrphy_dfi_p1_address[12]),
	.D4(a7ddrphy_dfi_p1_address[12]),
	.D5(a7ddrphy_dfi_p2_address[12]),
	.D6(a7ddrphy_dfi_p2_address[12]),
	.D7(a7ddrphy_dfi_p3_address[12]),
	.D8(a7ddrphy_dfi_p3_address[12]),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(ddram_a[12])
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_14 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_address[13]),
	.D2(a7ddrphy_dfi_p0_address[13]),
	.D3(a7ddrphy_dfi_p1_address[13]),
	.D4(a7ddrphy_dfi_p1_address[13]),
	.D5(a7ddrphy_dfi_p2_address[13]),
	.D6(a7ddrphy_dfi_p2_address[13]),
	.D7(a7ddrphy_dfi_p3_address[13]),
	.D8(a7ddrphy_dfi_p3_address[13]),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(ddram_a[13])
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_15 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_address[14]),
	.D2(a7ddrphy_dfi_p0_address[14]),
	.D3(a7ddrphy_dfi_p1_address[14]),
	.D4(a7ddrphy_dfi_p1_address[14]),
	.D5(a7ddrphy_dfi_p2_address[14]),
	.D6(a7ddrphy_dfi_p2_address[14]),
	.D7(a7ddrphy_dfi_p3_address[14]),
	.D8(a7ddrphy_dfi_p3_address[14]),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(ddram_a[14])
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_16 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_bank[0]),
	.D2(a7ddrphy_dfi_p0_bank[0]),
	.D3(a7ddrphy_dfi_p1_bank[0]),
	.D4(a7ddrphy_dfi_p1_bank[0]),
	.D5(a7ddrphy_dfi_p2_bank[0]),
	.D6(a7ddrphy_dfi_p2_bank[0]),
	.D7(a7ddrphy_dfi_p3_bank[0]),
	.D8(a7ddrphy_dfi_p3_bank[0]),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(ddram_ba[0])
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_17 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_bank[1]),
	.D2(a7ddrphy_dfi_p0_bank[1]),
	.D3(a7ddrphy_dfi_p1_bank[1]),
	.D4(a7ddrphy_dfi_p1_bank[1]),
	.D5(a7ddrphy_dfi_p2_bank[1]),
	.D6(a7ddrphy_dfi_p2_bank[1]),
	.D7(a7ddrphy_dfi_p3_bank[1]),
	.D8(a7ddrphy_dfi_p3_bank[1]),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(ddram_ba[1])
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_18 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_bank[2]),
	.D2(a7ddrphy_dfi_p0_bank[2]),
	.D3(a7ddrphy_dfi_p1_bank[2]),
	.D4(a7ddrphy_dfi_p1_bank[2]),
	.D5(a7ddrphy_dfi_p2_bank[2]),
	.D6(a7ddrphy_dfi_p2_bank[2]),
	.D7(a7ddrphy_dfi_p3_bank[2]),
	.D8(a7ddrphy_dfi_p3_bank[2]),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(ddram_ba[2])
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_19 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_ras_n),
	.D2(a7ddrphy_dfi_p0_ras_n),
	.D3(a7ddrphy_dfi_p1_ras_n),
	.D4(a7ddrphy_dfi_p1_ras_n),
	.D5(a7ddrphy_dfi_p2_ras_n),
	.D6(a7ddrphy_dfi_p2_ras_n),
	.D7(a7ddrphy_dfi_p3_ras_n),
	.D8(a7ddrphy_dfi_p3_ras_n),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(ddram_ras_n)
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_20 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_cas_n),
	.D2(a7ddrphy_dfi_p0_cas_n),
	.D3(a7ddrphy_dfi_p1_cas_n),
	.D4(a7ddrphy_dfi_p1_cas_n),
	.D5(a7ddrphy_dfi_p2_cas_n),
	.D6(a7ddrphy_dfi_p2_cas_n),
	.D7(a7ddrphy_dfi_p3_cas_n),
	.D8(a7ddrphy_dfi_p3_cas_n),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(ddram_cas_n)
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_21 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_we_n),
	.D2(a7ddrphy_dfi_p0_we_n),
	.D3(a7ddrphy_dfi_p1_we_n),
	.D4(a7ddrphy_dfi_p1_we_n),
	.D5(a7ddrphy_dfi_p2_we_n),
	.D6(a7ddrphy_dfi_p2_we_n),
	.D7(a7ddrphy_dfi_p3_we_n),
	.D8(a7ddrphy_dfi_p3_we_n),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(ddram_we_n)
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_22 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_cke),
	.D2(a7ddrphy_dfi_p0_cke),
	.D3(a7ddrphy_dfi_p1_cke),
	.D4(a7ddrphy_dfi_p1_cke),
	.D5(a7ddrphy_dfi_p2_cke),
	.D6(a7ddrphy_dfi_p2_cke),
	.D7(a7ddrphy_dfi_p3_cke),
	.D8(a7ddrphy_dfi_p3_cke),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(ddram_cke)
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_23 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_odt),
	.D2(a7ddrphy_dfi_p0_odt),
	.D3(a7ddrphy_dfi_p1_odt),
	.D4(a7ddrphy_dfi_p1_odt),
	.D5(a7ddrphy_dfi_p2_odt),
	.D6(a7ddrphy_dfi_p2_odt),
	.D7(a7ddrphy_dfi_p3_odt),
	.D8(a7ddrphy_dfi_p3_odt),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(ddram_odt)
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_24 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_reset_n),
	.D2(a7ddrphy_dfi_p0_reset_n),
	.D3(a7ddrphy_dfi_p1_reset_n),
	.D4(a7ddrphy_dfi_p1_reset_n),
	.D5(a7ddrphy_dfi_p2_reset_n),
	.D6(a7ddrphy_dfi_p2_reset_n),
	.D7(a7ddrphy_dfi_p3_reset_n),
	.D8(a7ddrphy_dfi_p3_reset_n),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(ddram_reset_n)
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_25 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_cs_n),
	.D2(a7ddrphy_dfi_p0_cs_n),
	.D3(a7ddrphy_dfi_p1_cs_n),
	.D4(a7ddrphy_dfi_p1_cs_n),
	.D5(a7ddrphy_dfi_p2_cs_n),
	.D6(a7ddrphy_dfi_p2_cs_n),
	.D7(a7ddrphy_dfi_p3_cs_n),
	.D8(a7ddrphy_dfi_p3_cs_n),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(ddram_cs_n)
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_26 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_wrdata_mask[0]),
	.D2(a7ddrphy_dfi_p0_wrdata_mask[2]),
	.D3(a7ddrphy_dfi_p1_wrdata_mask[0]),
	.D4(a7ddrphy_dfi_p1_wrdata_mask[2]),
	.D5(a7ddrphy_dfi_p2_wrdata_mask[0]),
	.D6(a7ddrphy_dfi_p2_wrdata_mask[2]),
	.D7(a7ddrphy_dfi_p3_wrdata_mask[0]),
	.D8(a7ddrphy_dfi_p3_wrdata_mask[2]),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(ddram_dm[0])
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_27 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_wrdata_mask[1]),
	.D2(a7ddrphy_dfi_p0_wrdata_mask[3]),
	.D3(a7ddrphy_dfi_p1_wrdata_mask[1]),
	.D4(a7ddrphy_dfi_p1_wrdata_mask[3]),
	.D5(a7ddrphy_dfi_p2_wrdata_mask[1]),
	.D6(a7ddrphy_dfi_p2_wrdata_mask[3]),
	.D7(a7ddrphy_dfi_p3_wrdata_mask[1]),
	.D8(a7ddrphy_dfi_p3_wrdata_mask[3]),
	.OCE(1'd1),
	.RST(sys_rst),
	.OQ(ddram_dm[1])
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_28 (
	.CLK(sys4x_dqs_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dqspattern_o1[0]),
	.D2(a7ddrphy_dqspattern_o1[1]),
	.D3(a7ddrphy_dqspattern_o1[2]),
	.D4(a7ddrphy_dqspattern_o1[3]),
	.D5(a7ddrphy_dqspattern_o1[4]),
	.D6(a7ddrphy_dqspattern_o1[5]),
	.D7(a7ddrphy_dqspattern_o1[6]),
	.D8(a7ddrphy_dqspattern_o1[7]),
	.OCE(1'd1),
	.RST(sys_rst),
	.T1((~a7ddrphy_dqs_oe_delayed)),
	.TCE(1'd1),
	.OFB(a7ddrphy0),
	.OQ(a7ddrphy_dqs_o_no_delay0),
	.TQ(a7ddrphy_dqs_t0)
);

IDELAYE2 #(
	.CINVCTRL_SEL("FALSE"),
	.DELAY_SRC("IDATAIN"),
	.HIGH_PERFORMANCE_MODE("TRUE"),
	.IDELAY_TYPE("FIXED"),
	.IDELAY_VALUE(4'd8),
	.PIPE_SEL("FALSE"),
	.REFCLK_FREQUENCY(200.0),
	.SIGNAL_PATTERN("DATA")
) IDELAYE2 (
	.IDATAIN(a7ddrphy_dqs_i[0]),
	.DATAOUT(a7ddrphy_dqs_i_delayed[0])
);

IOBUFDS IOBUFDS(
	.I(a7ddrphy_dqs_o_no_delay0),
	.T(a7ddrphy_dqs_t0),
	.IO(ddram_dqs_p[0]),
	.IOB(ddram_dqs_n[0]),
	.O(a7ddrphy_dqs_i[0])
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_29 (
	.CLK(sys4x_dqs_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dqspattern_o1[0]),
	.D2(a7ddrphy_dqspattern_o1[1]),
	.D3(a7ddrphy_dqspattern_o1[2]),
	.D4(a7ddrphy_dqspattern_o1[3]),
	.D5(a7ddrphy_dqspattern_o1[4]),
	.D6(a7ddrphy_dqspattern_o1[5]),
	.D7(a7ddrphy_dqspattern_o1[6]),
	.D8(a7ddrphy_dqspattern_o1[7]),
	.OCE(1'd1),
	.RST(sys_rst),
	.T1((~a7ddrphy_dqs_oe_delayed)),
	.TCE(1'd1),
	.OFB(a7ddrphy1),
	.OQ(a7ddrphy_dqs_o_no_delay1),
	.TQ(a7ddrphy_dqs_t1)
);

IDELAYE2 #(
	.CINVCTRL_SEL("FALSE"),
	.DELAY_SRC("IDATAIN"),
	.HIGH_PERFORMANCE_MODE("TRUE"),
	.IDELAY_TYPE("FIXED"),
	.IDELAY_VALUE(4'd8),
	.PIPE_SEL("FALSE"),
	.REFCLK_FREQUENCY(200.0),
	.SIGNAL_PATTERN("DATA")
) IDELAYE2_1 (
	.IDATAIN(a7ddrphy_dqs_i[1]),
	.DATAOUT(a7ddrphy_dqs_i_delayed[1])
);

IOBUFDS IOBUFDS_1(
	.I(a7ddrphy_dqs_o_no_delay1),
	.T(a7ddrphy_dqs_t1),
	.IO(ddram_dqs_p[1]),
	.IOB(ddram_dqs_n[1]),
	.O(a7ddrphy_dqs_i[1])
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_30 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_wrdata[0]),
	.D2(a7ddrphy_dfi_p0_wrdata[16]),
	.D3(a7ddrphy_dfi_p1_wrdata[0]),
	.D4(a7ddrphy_dfi_p1_wrdata[16]),
	.D5(a7ddrphy_dfi_p2_wrdata[0]),
	.D6(a7ddrphy_dfi_p2_wrdata[16]),
	.D7(a7ddrphy_dfi_p3_wrdata[0]),
	.D8(a7ddrphy_dfi_p3_wrdata[16]),
	.OCE(1'd1),
	.RST(sys_rst),
	.T1((~a7ddrphy_dq_oe_delayed)),
	.TCE(1'd1),
	.OQ(a7ddrphy_dq_o_nodelay0),
	.TQ(a7ddrphy_dq_t0)
);

ISERDESE2 #(
	.DATA_RATE("DDR"),
	.DATA_WIDTH(4'd8),
	.INTERFACE_TYPE("NETWORKING"),
	.IOBDELAY("IFD"),
	.NUM_CE(1'd1),
	.SERDES_MODE("MASTER")
) ISERDESE2 (
	.BITSLIP(1'd0),
	.CE1(1'd1),
	.CLK(sys4x_clk),
	.CLKB((~sys4x_clk)),
	.CLKDIV(sys_clk),
	.DDLY(a7ddrphy_dq_i_delayed0),
	.RST(sys_rst),
	.Q1(a7ddrphy_dq_i_data0[7]),
	.Q2(a7ddrphy_dq_i_data0[6]),
	.Q3(a7ddrphy_dq_i_data0[5]),
	.Q4(a7ddrphy_dq_i_data0[4]),
	.Q5(a7ddrphy_dq_i_data0[3]),
	.Q6(a7ddrphy_dq_i_data0[2]),
	.Q7(a7ddrphy_dq_i_data0[1]),
	.Q8(a7ddrphy_dq_i_data0[0])
);

IDELAYE2 #(
	.CINVCTRL_SEL("FALSE"),
	.DELAY_SRC("IDATAIN"),
	.HIGH_PERFORMANCE_MODE("TRUE"),
	.IDELAY_TYPE("VARIABLE"),
	.IDELAY_VALUE(1'd0),
	.PIPE_SEL("FALSE"),
	.REFCLK_FREQUENCY(200.0),
	.SIGNAL_PATTERN("DATA")
) IDELAYE2_2 (
	.C(sys_clk),
	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
	.IDATAIN(a7ddrphy_dq_i_nodelay0),
	.INC(1'd1),
	.LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
	.LDPIPEEN(1'd0),
	.DATAOUT(a7ddrphy_dq_i_delayed0)
);

IOBUF IOBUF(
	.I(a7ddrphy_dq_o_nodelay0),
	.T(a7ddrphy_dq_t0),
	.IO(ddram_dq[0]),
	.O(a7ddrphy_dq_i_nodelay0)
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_31 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_wrdata[1]),
	.D2(a7ddrphy_dfi_p0_wrdata[17]),
	.D3(a7ddrphy_dfi_p1_wrdata[1]),
	.D4(a7ddrphy_dfi_p1_wrdata[17]),
	.D5(a7ddrphy_dfi_p2_wrdata[1]),
	.D6(a7ddrphy_dfi_p2_wrdata[17]),
	.D7(a7ddrphy_dfi_p3_wrdata[1]),
	.D8(a7ddrphy_dfi_p3_wrdata[17]),
	.OCE(1'd1),
	.RST(sys_rst),
	.T1((~a7ddrphy_dq_oe_delayed)),
	.TCE(1'd1),
	.OQ(a7ddrphy_dq_o_nodelay1),
	.TQ(a7ddrphy_dq_t1)
);

ISERDESE2 #(
	.DATA_RATE("DDR"),
	.DATA_WIDTH(4'd8),
	.INTERFACE_TYPE("NETWORKING"),
	.IOBDELAY("IFD"),
	.NUM_CE(1'd1),
	.SERDES_MODE("MASTER")
) ISERDESE2_1 (
	.BITSLIP(1'd0),
	.CE1(1'd1),
	.CLK(sys4x_clk),
	.CLKB((~sys4x_clk)),
	.CLKDIV(sys_clk),
	.DDLY(a7ddrphy_dq_i_delayed1),
	.RST(sys_rst),
	.Q1(a7ddrphy_dq_i_data1[7]),
	.Q2(a7ddrphy_dq_i_data1[6]),
	.Q3(a7ddrphy_dq_i_data1[5]),
	.Q4(a7ddrphy_dq_i_data1[4]),
	.Q5(a7ddrphy_dq_i_data1[3]),
	.Q6(a7ddrphy_dq_i_data1[2]),
	.Q7(a7ddrphy_dq_i_data1[1]),
	.Q8(a7ddrphy_dq_i_data1[0])
);

IDELAYE2 #(
	.CINVCTRL_SEL("FALSE"),
	.DELAY_SRC("IDATAIN"),
	.HIGH_PERFORMANCE_MODE("TRUE"),
	.IDELAY_TYPE("VARIABLE"),
	.IDELAY_VALUE(1'd0),
	.PIPE_SEL("FALSE"),
	.REFCLK_FREQUENCY(200.0),
	.SIGNAL_PATTERN("DATA")
) IDELAYE2_3 (
	.C(sys_clk),
	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
	.IDATAIN(a7ddrphy_dq_i_nodelay1),
	.INC(1'd1),
	.LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
	.LDPIPEEN(1'd0),
	.DATAOUT(a7ddrphy_dq_i_delayed1)
);

IOBUF IOBUF_1(
	.I(a7ddrphy_dq_o_nodelay1),
	.T(a7ddrphy_dq_t1),
	.IO(ddram_dq[1]),
	.O(a7ddrphy_dq_i_nodelay1)
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_32 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_wrdata[2]),
	.D2(a7ddrphy_dfi_p0_wrdata[18]),
	.D3(a7ddrphy_dfi_p1_wrdata[2]),
	.D4(a7ddrphy_dfi_p1_wrdata[18]),
	.D5(a7ddrphy_dfi_p2_wrdata[2]),
	.D6(a7ddrphy_dfi_p2_wrdata[18]),
	.D7(a7ddrphy_dfi_p3_wrdata[2]),
	.D8(a7ddrphy_dfi_p3_wrdata[18]),
	.OCE(1'd1),
	.RST(sys_rst),
	.T1((~a7ddrphy_dq_oe_delayed)),
	.TCE(1'd1),
	.OQ(a7ddrphy_dq_o_nodelay2),
	.TQ(a7ddrphy_dq_t2)
);

ISERDESE2 #(
	.DATA_RATE("DDR"),
	.DATA_WIDTH(4'd8),
	.INTERFACE_TYPE("NETWORKING"),
	.IOBDELAY("IFD"),
	.NUM_CE(1'd1),
	.SERDES_MODE("MASTER")
) ISERDESE2_2 (
	.BITSLIP(1'd0),
	.CE1(1'd1),
	.CLK(sys4x_clk),
	.CLKB((~sys4x_clk)),
	.CLKDIV(sys_clk),
	.DDLY(a7ddrphy_dq_i_delayed2),
	.RST(sys_rst),
	.Q1(a7ddrphy_dq_i_data2[7]),
	.Q2(a7ddrphy_dq_i_data2[6]),
	.Q3(a7ddrphy_dq_i_data2[5]),
	.Q4(a7ddrphy_dq_i_data2[4]),
	.Q5(a7ddrphy_dq_i_data2[3]),
	.Q6(a7ddrphy_dq_i_data2[2]),
	.Q7(a7ddrphy_dq_i_data2[1]),
	.Q8(a7ddrphy_dq_i_data2[0])
);

IDELAYE2 #(
	.CINVCTRL_SEL("FALSE"),
	.DELAY_SRC("IDATAIN"),
	.HIGH_PERFORMANCE_MODE("TRUE"),
	.IDELAY_TYPE("VARIABLE"),
	.IDELAY_VALUE(1'd0),
	.PIPE_SEL("FALSE"),
	.REFCLK_FREQUENCY(200.0),
	.SIGNAL_PATTERN("DATA")
) IDELAYE2_4 (
	.C(sys_clk),
	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
	.IDATAIN(a7ddrphy_dq_i_nodelay2),
	.INC(1'd1),
	.LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
	.LDPIPEEN(1'd0),
	.DATAOUT(a7ddrphy_dq_i_delayed2)
);

IOBUF IOBUF_2(
	.I(a7ddrphy_dq_o_nodelay2),
	.T(a7ddrphy_dq_t2),
	.IO(ddram_dq[2]),
	.O(a7ddrphy_dq_i_nodelay2)
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_33 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_wrdata[3]),
	.D2(a7ddrphy_dfi_p0_wrdata[19]),
	.D3(a7ddrphy_dfi_p1_wrdata[3]),
	.D4(a7ddrphy_dfi_p1_wrdata[19]),
	.D5(a7ddrphy_dfi_p2_wrdata[3]),
	.D6(a7ddrphy_dfi_p2_wrdata[19]),
	.D7(a7ddrphy_dfi_p3_wrdata[3]),
	.D8(a7ddrphy_dfi_p3_wrdata[19]),
	.OCE(1'd1),
	.RST(sys_rst),
	.T1((~a7ddrphy_dq_oe_delayed)),
	.TCE(1'd1),
	.OQ(a7ddrphy_dq_o_nodelay3),
	.TQ(a7ddrphy_dq_t3)
);

ISERDESE2 #(
	.DATA_RATE("DDR"),
	.DATA_WIDTH(4'd8),
	.INTERFACE_TYPE("NETWORKING"),
	.IOBDELAY("IFD"),
	.NUM_CE(1'd1),
	.SERDES_MODE("MASTER")
) ISERDESE2_3 (
	.BITSLIP(1'd0),
	.CE1(1'd1),
	.CLK(sys4x_clk),
	.CLKB((~sys4x_clk)),
	.CLKDIV(sys_clk),
	.DDLY(a7ddrphy_dq_i_delayed3),
	.RST(sys_rst),
	.Q1(a7ddrphy_dq_i_data3[7]),
	.Q2(a7ddrphy_dq_i_data3[6]),
	.Q3(a7ddrphy_dq_i_data3[5]),
	.Q4(a7ddrphy_dq_i_data3[4]),
	.Q5(a7ddrphy_dq_i_data3[3]),
	.Q6(a7ddrphy_dq_i_data3[2]),
	.Q7(a7ddrphy_dq_i_data3[1]),
	.Q8(a7ddrphy_dq_i_data3[0])
);

IDELAYE2 #(
	.CINVCTRL_SEL("FALSE"),
	.DELAY_SRC("IDATAIN"),
	.HIGH_PERFORMANCE_MODE("TRUE"),
	.IDELAY_TYPE("VARIABLE"),
	.IDELAY_VALUE(1'd0),
	.PIPE_SEL("FALSE"),
	.REFCLK_FREQUENCY(200.0),
	.SIGNAL_PATTERN("DATA")
) IDELAYE2_5 (
	.C(sys_clk),
	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
	.IDATAIN(a7ddrphy_dq_i_nodelay3),
	.INC(1'd1),
	.LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
	.LDPIPEEN(1'd0),
	.DATAOUT(a7ddrphy_dq_i_delayed3)
);

IOBUF IOBUF_3(
	.I(a7ddrphy_dq_o_nodelay3),
	.T(a7ddrphy_dq_t3),
	.IO(ddram_dq[3]),
	.O(a7ddrphy_dq_i_nodelay3)
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_34 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_wrdata[4]),
	.D2(a7ddrphy_dfi_p0_wrdata[20]),
	.D3(a7ddrphy_dfi_p1_wrdata[4]),
	.D4(a7ddrphy_dfi_p1_wrdata[20]),
	.D5(a7ddrphy_dfi_p2_wrdata[4]),
	.D6(a7ddrphy_dfi_p2_wrdata[20]),
	.D7(a7ddrphy_dfi_p3_wrdata[4]),
	.D8(a7ddrphy_dfi_p3_wrdata[20]),
	.OCE(1'd1),
	.RST(sys_rst),
	.T1((~a7ddrphy_dq_oe_delayed)),
	.TCE(1'd1),
	.OQ(a7ddrphy_dq_o_nodelay4),
	.TQ(a7ddrphy_dq_t4)
);

ISERDESE2 #(
	.DATA_RATE("DDR"),
	.DATA_WIDTH(4'd8),
	.INTERFACE_TYPE("NETWORKING"),
	.IOBDELAY("IFD"),
	.NUM_CE(1'd1),
	.SERDES_MODE("MASTER")
) ISERDESE2_4 (
	.BITSLIP(1'd0),
	.CE1(1'd1),
	.CLK(sys4x_clk),
	.CLKB((~sys4x_clk)),
	.CLKDIV(sys_clk),
	.DDLY(a7ddrphy_dq_i_delayed4),
	.RST(sys_rst),
	.Q1(a7ddrphy_dq_i_data4[7]),
	.Q2(a7ddrphy_dq_i_data4[6]),
	.Q3(a7ddrphy_dq_i_data4[5]),
	.Q4(a7ddrphy_dq_i_data4[4]),
	.Q5(a7ddrphy_dq_i_data4[3]),
	.Q6(a7ddrphy_dq_i_data4[2]),
	.Q7(a7ddrphy_dq_i_data4[1]),
	.Q8(a7ddrphy_dq_i_data4[0])
);

IDELAYE2 #(
	.CINVCTRL_SEL("FALSE"),
	.DELAY_SRC("IDATAIN"),
	.HIGH_PERFORMANCE_MODE("TRUE"),
	.IDELAY_TYPE("VARIABLE"),
	.IDELAY_VALUE(1'd0),
	.PIPE_SEL("FALSE"),
	.REFCLK_FREQUENCY(200.0),
	.SIGNAL_PATTERN("DATA")
) IDELAYE2_6 (
	.C(sys_clk),
	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
	.IDATAIN(a7ddrphy_dq_i_nodelay4),
	.INC(1'd1),
	.LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
	.LDPIPEEN(1'd0),
	.DATAOUT(a7ddrphy_dq_i_delayed4)
);

IOBUF IOBUF_4(
	.I(a7ddrphy_dq_o_nodelay4),
	.T(a7ddrphy_dq_t4),
	.IO(ddram_dq[4]),
	.O(a7ddrphy_dq_i_nodelay4)
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_35 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_wrdata[5]),
	.D2(a7ddrphy_dfi_p0_wrdata[21]),
	.D3(a7ddrphy_dfi_p1_wrdata[5]),
	.D4(a7ddrphy_dfi_p1_wrdata[21]),
	.D5(a7ddrphy_dfi_p2_wrdata[5]),
	.D6(a7ddrphy_dfi_p2_wrdata[21]),
	.D7(a7ddrphy_dfi_p3_wrdata[5]),
	.D8(a7ddrphy_dfi_p3_wrdata[21]),
	.OCE(1'd1),
	.RST(sys_rst),
	.T1((~a7ddrphy_dq_oe_delayed)),
	.TCE(1'd1),
	.OQ(a7ddrphy_dq_o_nodelay5),
	.TQ(a7ddrphy_dq_t5)
);

ISERDESE2 #(
	.DATA_RATE("DDR"),
	.DATA_WIDTH(4'd8),
	.INTERFACE_TYPE("NETWORKING"),
	.IOBDELAY("IFD"),
	.NUM_CE(1'd1),
	.SERDES_MODE("MASTER")
) ISERDESE2_5 (
	.BITSLIP(1'd0),
	.CE1(1'd1),
	.CLK(sys4x_clk),
	.CLKB((~sys4x_clk)),
	.CLKDIV(sys_clk),
	.DDLY(a7ddrphy_dq_i_delayed5),
	.RST(sys_rst),
	.Q1(a7ddrphy_dq_i_data5[7]),
	.Q2(a7ddrphy_dq_i_data5[6]),
	.Q3(a7ddrphy_dq_i_data5[5]),
	.Q4(a7ddrphy_dq_i_data5[4]),
	.Q5(a7ddrphy_dq_i_data5[3]),
	.Q6(a7ddrphy_dq_i_data5[2]),
	.Q7(a7ddrphy_dq_i_data5[1]),
	.Q8(a7ddrphy_dq_i_data5[0])
);

IDELAYE2 #(
	.CINVCTRL_SEL("FALSE"),
	.DELAY_SRC("IDATAIN"),
	.HIGH_PERFORMANCE_MODE("TRUE"),
	.IDELAY_TYPE("VARIABLE"),
	.IDELAY_VALUE(1'd0),
	.PIPE_SEL("FALSE"),
	.REFCLK_FREQUENCY(200.0),
	.SIGNAL_PATTERN("DATA")
) IDELAYE2_7 (
	.C(sys_clk),
	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
	.IDATAIN(a7ddrphy_dq_i_nodelay5),
	.INC(1'd1),
	.LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
	.LDPIPEEN(1'd0),
	.DATAOUT(a7ddrphy_dq_i_delayed5)
);

IOBUF IOBUF_5(
	.I(a7ddrphy_dq_o_nodelay5),
	.T(a7ddrphy_dq_t5),
	.IO(ddram_dq[5]),
	.O(a7ddrphy_dq_i_nodelay5)
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_36 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_wrdata[6]),
	.D2(a7ddrphy_dfi_p0_wrdata[22]),
	.D3(a7ddrphy_dfi_p1_wrdata[6]),
	.D4(a7ddrphy_dfi_p1_wrdata[22]),
	.D5(a7ddrphy_dfi_p2_wrdata[6]),
	.D6(a7ddrphy_dfi_p2_wrdata[22]),
	.D7(a7ddrphy_dfi_p3_wrdata[6]),
	.D8(a7ddrphy_dfi_p3_wrdata[22]),
	.OCE(1'd1),
	.RST(sys_rst),
	.T1((~a7ddrphy_dq_oe_delayed)),
	.TCE(1'd1),
	.OQ(a7ddrphy_dq_o_nodelay6),
	.TQ(a7ddrphy_dq_t6)
);

ISERDESE2 #(
	.DATA_RATE("DDR"),
	.DATA_WIDTH(4'd8),
	.INTERFACE_TYPE("NETWORKING"),
	.IOBDELAY("IFD"),
	.NUM_CE(1'd1),
	.SERDES_MODE("MASTER")
) ISERDESE2_6 (
	.BITSLIP(1'd0),
	.CE1(1'd1),
	.CLK(sys4x_clk),
	.CLKB((~sys4x_clk)),
	.CLKDIV(sys_clk),
	.DDLY(a7ddrphy_dq_i_delayed6),
	.RST(sys_rst),
	.Q1(a7ddrphy_dq_i_data6[7]),
	.Q2(a7ddrphy_dq_i_data6[6]),
	.Q3(a7ddrphy_dq_i_data6[5]),
	.Q4(a7ddrphy_dq_i_data6[4]),
	.Q5(a7ddrphy_dq_i_data6[3]),
	.Q6(a7ddrphy_dq_i_data6[2]),
	.Q7(a7ddrphy_dq_i_data6[1]),
	.Q8(a7ddrphy_dq_i_data6[0])
);

IDELAYE2 #(
	.CINVCTRL_SEL("FALSE"),
	.DELAY_SRC("IDATAIN"),
	.HIGH_PERFORMANCE_MODE("TRUE"),
	.IDELAY_TYPE("VARIABLE"),
	.IDELAY_VALUE(1'd0),
	.PIPE_SEL("FALSE"),
	.REFCLK_FREQUENCY(200.0),
	.SIGNAL_PATTERN("DATA")
) IDELAYE2_8 (
	.C(sys_clk),
	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
	.IDATAIN(a7ddrphy_dq_i_nodelay6),
	.INC(1'd1),
	.LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
	.LDPIPEEN(1'd0),
	.DATAOUT(a7ddrphy_dq_i_delayed6)
);

IOBUF IOBUF_6(
	.I(a7ddrphy_dq_o_nodelay6),
	.T(a7ddrphy_dq_t6),
	.IO(ddram_dq[6]),
	.O(a7ddrphy_dq_i_nodelay6)
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_37 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_wrdata[7]),
	.D2(a7ddrphy_dfi_p0_wrdata[23]),
	.D3(a7ddrphy_dfi_p1_wrdata[7]),
	.D4(a7ddrphy_dfi_p1_wrdata[23]),
	.D5(a7ddrphy_dfi_p2_wrdata[7]),
	.D6(a7ddrphy_dfi_p2_wrdata[23]),
	.D7(a7ddrphy_dfi_p3_wrdata[7]),
	.D8(a7ddrphy_dfi_p3_wrdata[23]),
	.OCE(1'd1),
	.RST(sys_rst),
	.T1((~a7ddrphy_dq_oe_delayed)),
	.TCE(1'd1),
	.OQ(a7ddrphy_dq_o_nodelay7),
	.TQ(a7ddrphy_dq_t7)
);

ISERDESE2 #(
	.DATA_RATE("DDR"),
	.DATA_WIDTH(4'd8),
	.INTERFACE_TYPE("NETWORKING"),
	.IOBDELAY("IFD"),
	.NUM_CE(1'd1),
	.SERDES_MODE("MASTER")
) ISERDESE2_7 (
	.BITSLIP(1'd0),
	.CE1(1'd1),
	.CLK(sys4x_clk),
	.CLKB((~sys4x_clk)),
	.CLKDIV(sys_clk),
	.DDLY(a7ddrphy_dq_i_delayed7),
	.RST(sys_rst),
	.Q1(a7ddrphy_dq_i_data7[7]),
	.Q2(a7ddrphy_dq_i_data7[6]),
	.Q3(a7ddrphy_dq_i_data7[5]),
	.Q4(a7ddrphy_dq_i_data7[4]),
	.Q5(a7ddrphy_dq_i_data7[3]),
	.Q6(a7ddrphy_dq_i_data7[2]),
	.Q7(a7ddrphy_dq_i_data7[1]),
	.Q8(a7ddrphy_dq_i_data7[0])
);

IDELAYE2 #(
	.CINVCTRL_SEL("FALSE"),
	.DELAY_SRC("IDATAIN"),
	.HIGH_PERFORMANCE_MODE("TRUE"),
	.IDELAY_TYPE("VARIABLE"),
	.IDELAY_VALUE(1'd0),
	.PIPE_SEL("FALSE"),
	.REFCLK_FREQUENCY(200.0),
	.SIGNAL_PATTERN("DATA")
) IDELAYE2_9 (
	.C(sys_clk),
	.CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
	.IDATAIN(a7ddrphy_dq_i_nodelay7),
	.INC(1'd1),
	.LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
	.LDPIPEEN(1'd0),
	.DATAOUT(a7ddrphy_dq_i_delayed7)
);

IOBUF IOBUF_7(
	.I(a7ddrphy_dq_o_nodelay7),
	.T(a7ddrphy_dq_t7),
	.IO(ddram_dq[7]),
	.O(a7ddrphy_dq_i_nodelay7)
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_38 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_wrdata[8]),
	.D2(a7ddrphy_dfi_p0_wrdata[24]),
	.D3(a7ddrphy_dfi_p1_wrdata[8]),
	.D4(a7ddrphy_dfi_p1_wrdata[24]),
	.D5(a7ddrphy_dfi_p2_wrdata[8]),
	.D6(a7ddrphy_dfi_p2_wrdata[24]),
	.D7(a7ddrphy_dfi_p3_wrdata[8]),
	.D8(a7ddrphy_dfi_p3_wrdata[24]),
	.OCE(1'd1),
	.RST(sys_rst),
	.T1((~a7ddrphy_dq_oe_delayed)),
	.TCE(1'd1),
	.OQ(a7ddrphy_dq_o_nodelay8),
	.TQ(a7ddrphy_dq_t8)
);

ISERDESE2 #(
	.DATA_RATE("DDR"),
	.DATA_WIDTH(4'd8),
	.INTERFACE_TYPE("NETWORKING"),
	.IOBDELAY("IFD"),
	.NUM_CE(1'd1),
	.SERDES_MODE("MASTER")
) ISERDESE2_8 (
	.BITSLIP(1'd0),
	.CE1(1'd1),
	.CLK(sys4x_clk),
	.CLKB((~sys4x_clk)),
	.CLKDIV(sys_clk),
	.DDLY(a7ddrphy_dq_i_delayed8),
	.RST(sys_rst),
	.Q1(a7ddrphy_dq_i_data8[7]),
	.Q2(a7ddrphy_dq_i_data8[6]),
	.Q3(a7ddrphy_dq_i_data8[5]),
	.Q4(a7ddrphy_dq_i_data8[4]),
	.Q5(a7ddrphy_dq_i_data8[3]),
	.Q6(a7ddrphy_dq_i_data8[2]),
	.Q7(a7ddrphy_dq_i_data8[1]),
	.Q8(a7ddrphy_dq_i_data8[0])
);

IDELAYE2 #(
	.CINVCTRL_SEL("FALSE"),
	.DELAY_SRC("IDATAIN"),
	.HIGH_PERFORMANCE_MODE("TRUE"),
	.IDELAY_TYPE("VARIABLE"),
	.IDELAY_VALUE(1'd0),
	.PIPE_SEL("FALSE"),
	.REFCLK_FREQUENCY(200.0),
	.SIGNAL_PATTERN("DATA")
) IDELAYE2_10 (
	.C(sys_clk),
	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
	.IDATAIN(a7ddrphy_dq_i_nodelay8),
	.INC(1'd1),
	.LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
	.LDPIPEEN(1'd0),
	.DATAOUT(a7ddrphy_dq_i_delayed8)
);

IOBUF IOBUF_8(
	.I(a7ddrphy_dq_o_nodelay8),
	.T(a7ddrphy_dq_t8),
	.IO(ddram_dq[8]),
	.O(a7ddrphy_dq_i_nodelay8)
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_39 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_wrdata[9]),
	.D2(a7ddrphy_dfi_p0_wrdata[25]),
	.D3(a7ddrphy_dfi_p1_wrdata[9]),
	.D4(a7ddrphy_dfi_p1_wrdata[25]),
	.D5(a7ddrphy_dfi_p2_wrdata[9]),
	.D6(a7ddrphy_dfi_p2_wrdata[25]),
	.D7(a7ddrphy_dfi_p3_wrdata[9]),
	.D8(a7ddrphy_dfi_p3_wrdata[25]),
	.OCE(1'd1),
	.RST(sys_rst),
	.T1((~a7ddrphy_dq_oe_delayed)),
	.TCE(1'd1),
	.OQ(a7ddrphy_dq_o_nodelay9),
	.TQ(a7ddrphy_dq_t9)
);

ISERDESE2 #(
	.DATA_RATE("DDR"),
	.DATA_WIDTH(4'd8),
	.INTERFACE_TYPE("NETWORKING"),
	.IOBDELAY("IFD"),
	.NUM_CE(1'd1),
	.SERDES_MODE("MASTER")
) ISERDESE2_9 (
	.BITSLIP(1'd0),
	.CE1(1'd1),
	.CLK(sys4x_clk),
	.CLKB((~sys4x_clk)),
	.CLKDIV(sys_clk),
	.DDLY(a7ddrphy_dq_i_delayed9),
	.RST(sys_rst),
	.Q1(a7ddrphy_dq_i_data9[7]),
	.Q2(a7ddrphy_dq_i_data9[6]),
	.Q3(a7ddrphy_dq_i_data9[5]),
	.Q4(a7ddrphy_dq_i_data9[4]),
	.Q5(a7ddrphy_dq_i_data9[3]),
	.Q6(a7ddrphy_dq_i_data9[2]),
	.Q7(a7ddrphy_dq_i_data9[1]),
	.Q8(a7ddrphy_dq_i_data9[0])
);

IDELAYE2 #(
	.CINVCTRL_SEL("FALSE"),
	.DELAY_SRC("IDATAIN"),
	.HIGH_PERFORMANCE_MODE("TRUE"),
	.IDELAY_TYPE("VARIABLE"),
	.IDELAY_VALUE(1'd0),
	.PIPE_SEL("FALSE"),
	.REFCLK_FREQUENCY(200.0),
	.SIGNAL_PATTERN("DATA")
) IDELAYE2_11 (
	.C(sys_clk),
	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
	.IDATAIN(a7ddrphy_dq_i_nodelay9),
	.INC(1'd1),
	.LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
	.LDPIPEEN(1'd0),
	.DATAOUT(a7ddrphy_dq_i_delayed9)
);

IOBUF IOBUF_9(
	.I(a7ddrphy_dq_o_nodelay9),
	.T(a7ddrphy_dq_t9),
	.IO(ddram_dq[9]),
	.O(a7ddrphy_dq_i_nodelay9)
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_40 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_wrdata[10]),
	.D2(a7ddrphy_dfi_p0_wrdata[26]),
	.D3(a7ddrphy_dfi_p1_wrdata[10]),
	.D4(a7ddrphy_dfi_p1_wrdata[26]),
	.D5(a7ddrphy_dfi_p2_wrdata[10]),
	.D6(a7ddrphy_dfi_p2_wrdata[26]),
	.D7(a7ddrphy_dfi_p3_wrdata[10]),
	.D8(a7ddrphy_dfi_p3_wrdata[26]),
	.OCE(1'd1),
	.RST(sys_rst),
	.T1((~a7ddrphy_dq_oe_delayed)),
	.TCE(1'd1),
	.OQ(a7ddrphy_dq_o_nodelay10),
	.TQ(a7ddrphy_dq_t10)
);

ISERDESE2 #(
	.DATA_RATE("DDR"),
	.DATA_WIDTH(4'd8),
	.INTERFACE_TYPE("NETWORKING"),
	.IOBDELAY("IFD"),
	.NUM_CE(1'd1),
	.SERDES_MODE("MASTER")
) ISERDESE2_10 (
	.BITSLIP(1'd0),
	.CE1(1'd1),
	.CLK(sys4x_clk),
	.CLKB((~sys4x_clk)),
	.CLKDIV(sys_clk),
	.DDLY(a7ddrphy_dq_i_delayed10),
	.RST(sys_rst),
	.Q1(a7ddrphy_dq_i_data10[7]),
	.Q2(a7ddrphy_dq_i_data10[6]),
	.Q3(a7ddrphy_dq_i_data10[5]),
	.Q4(a7ddrphy_dq_i_data10[4]),
	.Q5(a7ddrphy_dq_i_data10[3]),
	.Q6(a7ddrphy_dq_i_data10[2]),
	.Q7(a7ddrphy_dq_i_data10[1]),
	.Q8(a7ddrphy_dq_i_data10[0])
);

IDELAYE2 #(
	.CINVCTRL_SEL("FALSE"),
	.DELAY_SRC("IDATAIN"),
	.HIGH_PERFORMANCE_MODE("TRUE"),
	.IDELAY_TYPE("VARIABLE"),
	.IDELAY_VALUE(1'd0),
	.PIPE_SEL("FALSE"),
	.REFCLK_FREQUENCY(200.0),
	.SIGNAL_PATTERN("DATA")
) IDELAYE2_12 (
	.C(sys_clk),
	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
	.IDATAIN(a7ddrphy_dq_i_nodelay10),
	.INC(1'd1),
	.LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
	.LDPIPEEN(1'd0),
	.DATAOUT(a7ddrphy_dq_i_delayed10)
);

IOBUF IOBUF_10(
	.I(a7ddrphy_dq_o_nodelay10),
	.T(a7ddrphy_dq_t10),
	.IO(ddram_dq[10]),
	.O(a7ddrphy_dq_i_nodelay10)
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_41 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_wrdata[11]),
	.D2(a7ddrphy_dfi_p0_wrdata[27]),
	.D3(a7ddrphy_dfi_p1_wrdata[11]),
	.D4(a7ddrphy_dfi_p1_wrdata[27]),
	.D5(a7ddrphy_dfi_p2_wrdata[11]),
	.D6(a7ddrphy_dfi_p2_wrdata[27]),
	.D7(a7ddrphy_dfi_p3_wrdata[11]),
	.D8(a7ddrphy_dfi_p3_wrdata[27]),
	.OCE(1'd1),
	.RST(sys_rst),
	.T1((~a7ddrphy_dq_oe_delayed)),
	.TCE(1'd1),
	.OQ(a7ddrphy_dq_o_nodelay11),
	.TQ(a7ddrphy_dq_t11)
);

ISERDESE2 #(
	.DATA_RATE("DDR"),
	.DATA_WIDTH(4'd8),
	.INTERFACE_TYPE("NETWORKING"),
	.IOBDELAY("IFD"),
	.NUM_CE(1'd1),
	.SERDES_MODE("MASTER")
) ISERDESE2_11 (
	.BITSLIP(1'd0),
	.CE1(1'd1),
	.CLK(sys4x_clk),
	.CLKB((~sys4x_clk)),
	.CLKDIV(sys_clk),
	.DDLY(a7ddrphy_dq_i_delayed11),
	.RST(sys_rst),
	.Q1(a7ddrphy_dq_i_data11[7]),
	.Q2(a7ddrphy_dq_i_data11[6]),
	.Q3(a7ddrphy_dq_i_data11[5]),
	.Q4(a7ddrphy_dq_i_data11[4]),
	.Q5(a7ddrphy_dq_i_data11[3]),
	.Q6(a7ddrphy_dq_i_data11[2]),
	.Q7(a7ddrphy_dq_i_data11[1]),
	.Q8(a7ddrphy_dq_i_data11[0])
);

IDELAYE2 #(
	.CINVCTRL_SEL("FALSE"),
	.DELAY_SRC("IDATAIN"),
	.HIGH_PERFORMANCE_MODE("TRUE"),
	.IDELAY_TYPE("VARIABLE"),
	.IDELAY_VALUE(1'd0),
	.PIPE_SEL("FALSE"),
	.REFCLK_FREQUENCY(200.0),
	.SIGNAL_PATTERN("DATA")
) IDELAYE2_13 (
	.C(sys_clk),
	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
	.IDATAIN(a7ddrphy_dq_i_nodelay11),
	.INC(1'd1),
	.LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
	.LDPIPEEN(1'd0),
	.DATAOUT(a7ddrphy_dq_i_delayed11)
);

IOBUF IOBUF_11(
	.I(a7ddrphy_dq_o_nodelay11),
	.T(a7ddrphy_dq_t11),
	.IO(ddram_dq[11]),
	.O(a7ddrphy_dq_i_nodelay11)
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_42 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_wrdata[12]),
	.D2(a7ddrphy_dfi_p0_wrdata[28]),
	.D3(a7ddrphy_dfi_p1_wrdata[12]),
	.D4(a7ddrphy_dfi_p1_wrdata[28]),
	.D5(a7ddrphy_dfi_p2_wrdata[12]),
	.D6(a7ddrphy_dfi_p2_wrdata[28]),
	.D7(a7ddrphy_dfi_p3_wrdata[12]),
	.D8(a7ddrphy_dfi_p3_wrdata[28]),
	.OCE(1'd1),
	.RST(sys_rst),
	.T1((~a7ddrphy_dq_oe_delayed)),
	.TCE(1'd1),
	.OQ(a7ddrphy_dq_o_nodelay12),
	.TQ(a7ddrphy_dq_t12)
);

ISERDESE2 #(
	.DATA_RATE("DDR"),
	.DATA_WIDTH(4'd8),
	.INTERFACE_TYPE("NETWORKING"),
	.IOBDELAY("IFD"),
	.NUM_CE(1'd1),
	.SERDES_MODE("MASTER")
) ISERDESE2_12 (
	.BITSLIP(1'd0),
	.CE1(1'd1),
	.CLK(sys4x_clk),
	.CLKB((~sys4x_clk)),
	.CLKDIV(sys_clk),
	.DDLY(a7ddrphy_dq_i_delayed12),
	.RST(sys_rst),
	.Q1(a7ddrphy_dq_i_data12[7]),
	.Q2(a7ddrphy_dq_i_data12[6]),
	.Q3(a7ddrphy_dq_i_data12[5]),
	.Q4(a7ddrphy_dq_i_data12[4]),
	.Q5(a7ddrphy_dq_i_data12[3]),
	.Q6(a7ddrphy_dq_i_data12[2]),
	.Q7(a7ddrphy_dq_i_data12[1]),
	.Q8(a7ddrphy_dq_i_data12[0])
);

IDELAYE2 #(
	.CINVCTRL_SEL("FALSE"),
	.DELAY_SRC("IDATAIN"),
	.HIGH_PERFORMANCE_MODE("TRUE"),
	.IDELAY_TYPE("VARIABLE"),
	.IDELAY_VALUE(1'd0),
	.PIPE_SEL("FALSE"),
	.REFCLK_FREQUENCY(200.0),
	.SIGNAL_PATTERN("DATA")
) IDELAYE2_14 (
	.C(sys_clk),
	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
	.IDATAIN(a7ddrphy_dq_i_nodelay12),
	.INC(1'd1),
	.LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
	.LDPIPEEN(1'd0),
	.DATAOUT(a7ddrphy_dq_i_delayed12)
);

IOBUF IOBUF_12(
	.I(a7ddrphy_dq_o_nodelay12),
	.T(a7ddrphy_dq_t12),
	.IO(ddram_dq[12]),
	.O(a7ddrphy_dq_i_nodelay12)
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_43 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_wrdata[13]),
	.D2(a7ddrphy_dfi_p0_wrdata[29]),
	.D3(a7ddrphy_dfi_p1_wrdata[13]),
	.D4(a7ddrphy_dfi_p1_wrdata[29]),
	.D5(a7ddrphy_dfi_p2_wrdata[13]),
	.D6(a7ddrphy_dfi_p2_wrdata[29]),
	.D7(a7ddrphy_dfi_p3_wrdata[13]),
	.D8(a7ddrphy_dfi_p3_wrdata[29]),
	.OCE(1'd1),
	.RST(sys_rst),
	.T1((~a7ddrphy_dq_oe_delayed)),
	.TCE(1'd1),
	.OQ(a7ddrphy_dq_o_nodelay13),
	.TQ(a7ddrphy_dq_t13)
);

ISERDESE2 #(
	.DATA_RATE("DDR"),
	.DATA_WIDTH(4'd8),
	.INTERFACE_TYPE("NETWORKING"),
	.IOBDELAY("IFD"),
	.NUM_CE(1'd1),
	.SERDES_MODE("MASTER")
) ISERDESE2_13 (
	.BITSLIP(1'd0),
	.CE1(1'd1),
	.CLK(sys4x_clk),
	.CLKB((~sys4x_clk)),
	.CLKDIV(sys_clk),
	.DDLY(a7ddrphy_dq_i_delayed13),
	.RST(sys_rst),
	.Q1(a7ddrphy_dq_i_data13[7]),
	.Q2(a7ddrphy_dq_i_data13[6]),
	.Q3(a7ddrphy_dq_i_data13[5]),
	.Q4(a7ddrphy_dq_i_data13[4]),
	.Q5(a7ddrphy_dq_i_data13[3]),
	.Q6(a7ddrphy_dq_i_data13[2]),
	.Q7(a7ddrphy_dq_i_data13[1]),
	.Q8(a7ddrphy_dq_i_data13[0])
);

IDELAYE2 #(
	.CINVCTRL_SEL("FALSE"),
	.DELAY_SRC("IDATAIN"),
	.HIGH_PERFORMANCE_MODE("TRUE"),
	.IDELAY_TYPE("VARIABLE"),
	.IDELAY_VALUE(1'd0),
	.PIPE_SEL("FALSE"),
	.REFCLK_FREQUENCY(200.0),
	.SIGNAL_PATTERN("DATA")
) IDELAYE2_15 (
	.C(sys_clk),
	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
	.IDATAIN(a7ddrphy_dq_i_nodelay13),
	.INC(1'd1),
	.LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
	.LDPIPEEN(1'd0),
	.DATAOUT(a7ddrphy_dq_i_delayed13)
);

IOBUF IOBUF_13(
	.I(a7ddrphy_dq_o_nodelay13),
	.T(a7ddrphy_dq_t13),
	.IO(ddram_dq[13]),
	.O(a7ddrphy_dq_i_nodelay13)
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_44 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_wrdata[14]),
	.D2(a7ddrphy_dfi_p0_wrdata[30]),
	.D3(a7ddrphy_dfi_p1_wrdata[14]),
	.D4(a7ddrphy_dfi_p1_wrdata[30]),
	.D5(a7ddrphy_dfi_p2_wrdata[14]),
	.D6(a7ddrphy_dfi_p2_wrdata[30]),
	.D7(a7ddrphy_dfi_p3_wrdata[14]),
	.D8(a7ddrphy_dfi_p3_wrdata[30]),
	.OCE(1'd1),
	.RST(sys_rst),
	.T1((~a7ddrphy_dq_oe_delayed)),
	.TCE(1'd1),
	.OQ(a7ddrphy_dq_o_nodelay14),
	.TQ(a7ddrphy_dq_t14)
);

ISERDESE2 #(
	.DATA_RATE("DDR"),
	.DATA_WIDTH(4'd8),
	.INTERFACE_TYPE("NETWORKING"),
	.IOBDELAY("IFD"),
	.NUM_CE(1'd1),
	.SERDES_MODE("MASTER")
) ISERDESE2_14 (
	.BITSLIP(1'd0),
	.CE1(1'd1),
	.CLK(sys4x_clk),
	.CLKB((~sys4x_clk)),
	.CLKDIV(sys_clk),
	.DDLY(a7ddrphy_dq_i_delayed14),
	.RST(sys_rst),
	.Q1(a7ddrphy_dq_i_data14[7]),
	.Q2(a7ddrphy_dq_i_data14[6]),
	.Q3(a7ddrphy_dq_i_data14[5]),
	.Q4(a7ddrphy_dq_i_data14[4]),
	.Q5(a7ddrphy_dq_i_data14[3]),
	.Q6(a7ddrphy_dq_i_data14[2]),
	.Q7(a7ddrphy_dq_i_data14[1]),
	.Q8(a7ddrphy_dq_i_data14[0])
);

IDELAYE2 #(
	.CINVCTRL_SEL("FALSE"),
	.DELAY_SRC("IDATAIN"),
	.HIGH_PERFORMANCE_MODE("TRUE"),
	.IDELAY_TYPE("VARIABLE"),
	.IDELAY_VALUE(1'd0),
	.PIPE_SEL("FALSE"),
	.REFCLK_FREQUENCY(200.0),
	.SIGNAL_PATTERN("DATA")
) IDELAYE2_16 (
	.C(sys_clk),
	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
	.IDATAIN(a7ddrphy_dq_i_nodelay14),
	.INC(1'd1),
	.LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
	.LDPIPEEN(1'd0),
	.DATAOUT(a7ddrphy_dq_i_delayed14)
);

IOBUF IOBUF_14(
	.I(a7ddrphy_dq_o_nodelay14),
	.T(a7ddrphy_dq_t14),
	.IO(ddram_dq[14]),
	.O(a7ddrphy_dq_i_nodelay14)
);

OSERDESE2 #(
	.DATA_RATE_OQ("DDR"),
	.DATA_RATE_TQ("BUF"),
	.DATA_WIDTH(4'd8),
	.SERDES_MODE("MASTER"),
	.TRISTATE_WIDTH(1'd1)
) OSERDESE2_45 (
	.CLK(sys4x_clk),
	.CLKDIV(sys_clk),
	.D1(a7ddrphy_dfi_p0_wrdata[15]),
	.D2(a7ddrphy_dfi_p0_wrdata[31]),
	.D3(a7ddrphy_dfi_p1_wrdata[15]),
	.D4(a7ddrphy_dfi_p1_wrdata[31]),
	.D5(a7ddrphy_dfi_p2_wrdata[15]),
	.D6(a7ddrphy_dfi_p2_wrdata[31]),
	.D7(a7ddrphy_dfi_p3_wrdata[15]),
	.D8(a7ddrphy_dfi_p3_wrdata[31]),
	.OCE(1'd1),
	.RST(sys_rst),
	.T1((~a7ddrphy_dq_oe_delayed)),
	.TCE(1'd1),
	.OQ(a7ddrphy_dq_o_nodelay15),
	.TQ(a7ddrphy_dq_t15)
);

ISERDESE2 #(
	.DATA_RATE("DDR"),
	.DATA_WIDTH(4'd8),
	.INTERFACE_TYPE("NETWORKING"),
	.IOBDELAY("IFD"),
	.NUM_CE(1'd1),
	.SERDES_MODE("MASTER")
) ISERDESE2_15 (
	.BITSLIP(1'd0),
	.CE1(1'd1),
	.CLK(sys4x_clk),
	.CLKB((~sys4x_clk)),
	.CLKDIV(sys_clk),
	.DDLY(a7ddrphy_dq_i_delayed15),
	.RST(sys_rst),
	.Q1(a7ddrphy_dq_i_data15[7]),
	.Q2(a7ddrphy_dq_i_data15[6]),
	.Q3(a7ddrphy_dq_i_data15[5]),
	.Q4(a7ddrphy_dq_i_data15[4]),
	.Q5(a7ddrphy_dq_i_data15[3]),
	.Q6(a7ddrphy_dq_i_data15[2]),
	.Q7(a7ddrphy_dq_i_data15[1]),
	.Q8(a7ddrphy_dq_i_data15[0])
);

IDELAYE2 #(
	.CINVCTRL_SEL("FALSE"),
	.DELAY_SRC("IDATAIN"),
	.HIGH_PERFORMANCE_MODE("TRUE"),
	.IDELAY_TYPE("VARIABLE"),
	.IDELAY_VALUE(1'd0),
	.PIPE_SEL("FALSE"),
	.REFCLK_FREQUENCY(200.0),
	.SIGNAL_PATTERN("DATA")
) IDELAYE2_17 (
	.C(sys_clk),
	.CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
	.IDATAIN(a7ddrphy_dq_i_nodelay15),
	.INC(1'd1),
	.LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
	.LDPIPEEN(1'd0),
	.DATAOUT(a7ddrphy_dq_i_delayed15)
);

IOBUF IOBUF_15(
	.I(a7ddrphy_dq_o_nodelay15),
	.T(a7ddrphy_dq_t15),
	.IO(ddram_dq[15]),
	.O(a7ddrphy_dq_i_nodelay15)
);

reg [24:0] storage[0:15];
reg [24:0] memdat;
always @(posedge sys_clk) begin
	if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
		storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
	memdat <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
end

always @(posedge sys_clk) begin
end

assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];

reg [24:0] storage_1[0:15];
reg [24:0] memdat_1;
always @(posedge sys_clk) begin
	if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
		storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
	memdat_1 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
end

always @(posedge sys_clk) begin
end

assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];

reg [24:0] storage_2[0:15];
reg [24:0] memdat_2;
always @(posedge sys_clk) begin
	if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
		storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
	memdat_2 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
end

always @(posedge sys_clk) begin
end

assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];

reg [24:0] storage_3[0:15];
reg [24:0] memdat_3;
always @(posedge sys_clk) begin
	if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
		storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
	memdat_3 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
end

always @(posedge sys_clk) begin
end

assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];

reg [24:0] storage_4[0:15];
reg [24:0] memdat_4;
always @(posedge sys_clk) begin
	if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
		storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
	memdat_4 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
end

always @(posedge sys_clk) begin
end

assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];

reg [24:0] storage_5[0:15];
reg [24:0] memdat_5;
always @(posedge sys_clk) begin
	if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
		storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
	memdat_5 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
end

always @(posedge sys_clk) begin
end

assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];

reg [24:0] storage_6[0:15];
reg [24:0] memdat_6;
always @(posedge sys_clk) begin
	if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
		storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
	memdat_6 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
end

always @(posedge sys_clk) begin
end

assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];

reg [24:0] storage_7[0:15];
reg [24:0] memdat_7;
always @(posedge sys_clk) begin
	if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
		storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
	memdat_7 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
end

always @(posedge sys_clk) begin
end

assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];

PLLE2_ADV #(
	.CLKFBOUT_MULT(5'd16),
	.CLKIN1_PERIOD(10.0),
	.CLKOUT0_DIVIDE(5'd16),
	.CLKOUT0_PHASE(1'd0),
	.CLKOUT1_DIVIDE(3'd4),
	.CLKOUT1_PHASE(1'd0),
	.CLKOUT2_DIVIDE(3'd4),
	.CLKOUT2_PHASE(7'd90),
	.DIVCLK_DIVIDE(1'd1),
	.REF_JITTER1(0.01),
	.STARTUP_WAIT("FALSE")
) PLLE2_ADV (
	.CLKFBIN(pll_fb0),
	.CLKIN1(s7pll0_clkin),
	.RST(sys_pll_reset),
	.CLKFBOUT(pll_fb0),
	.CLKOUT0(s7pll0_clkout0),
	.CLKOUT1(s7pll0_clkout1),
	.CLKOUT2(s7pll0_clkout2),
	.LOCKED(sys_pll_locked)
);

PLLE2_ADV #(
	.CLKFBOUT_MULT(5'd16),
	.CLKIN1_PERIOD(10.0),
	.CLKOUT0_DIVIDE(4'd8),
	.CLKOUT0_PHASE(1'd0),
	.DIVCLK_DIVIDE(1'd1),
	.REF_JITTER1(0.01),
	.STARTUP_WAIT("FALSE")
) PLLE2_ADV_1 (
	.CLKFBIN(pll_fb1),
	.CLKIN1(s7pll1_clkin),
	.RST(iodelay_pll_reset),
	.CLKFBOUT(pll_fb1),
	.CLKOUT0(s7pll1_clkout),
	.LOCKED(iodelay_pll_locked)
);

(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
	.INIT(1'd1)
) FDPE (
	.C(sys_clk),
	.CE(1'd1),
	.D(1'd0),
	.PRE(xilinxasyncresetsynchronizerimpl0),
	.Q(xilinxasyncresetsynchronizerimpl0_rst_meta)
);

(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
	.INIT(1'd1)
) FDPE_1 (
	.C(sys_clk),
	.CE(1'd1),
	.D(xilinxasyncresetsynchronizerimpl0_rst_meta),
	.PRE(xilinxasyncresetsynchronizerimpl0),
	.Q(sys_rst)
);

(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
	.INIT(1'd1)
) FDPE_2 (
	.C(sys4x_clk),
	.CE(1'd1),
	.D(1'd0),
	.PRE(xilinxasyncresetsynchronizerimpl1),
	.Q(xilinxasyncresetsynchronizerimpl1_rst_meta)
);

(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
	.INIT(1'd1)
) FDPE_3 (
	.C(sys4x_clk),
	.CE(1'd1),
	.D(xilinxasyncresetsynchronizerimpl1_rst_meta),
	.PRE(xilinxasyncresetsynchronizerimpl1),
	.Q(xilinxasyncresetsynchronizerimpl1_expr)
);

(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
	.INIT(1'd1)
) FDPE_4 (
	.C(sys4x_dqs_clk),
	.CE(1'd1),
	.D(1'd0),
	.PRE(xilinxasyncresetsynchronizerimpl2),
	.Q(xilinxasyncresetsynchronizerimpl2_rst_meta)
);

(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
	.INIT(1'd1)
) FDPE_5 (
	.C(sys4x_dqs_clk),
	.CE(1'd1),
	.D(xilinxasyncresetsynchronizerimpl2_rst_meta),
	.PRE(xilinxasyncresetsynchronizerimpl2),
	.Q(xilinxasyncresetsynchronizerimpl2_expr)
);

(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
	.INIT(1'd1)
) FDPE_6 (
	.C(iodelay_clk),
	.CE(1'd1),
	.D(1'd0),
	.PRE(xilinxasyncresetsynchronizerimpl3),
	.Q(xilinxasyncresetsynchronizerimpl3_rst_meta)
);

(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
	.INIT(1'd1)
) FDPE_7 (
	.C(iodelay_clk),
	.CE(1'd1),
	.D(xilinxasyncresetsynchronizerimpl3_rst_meta),
	.PRE(xilinxasyncresetsynchronizerimpl3),
	.Q(iodelay_rst)
);

endmodule
