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https://github.com/antonblanchard/microwatt.git
synced 2026-01-11 23:43:15 +00:00
loadstore1: Do SPR reading in stage 2 rather than stage 3
This eliminates one leg of the output value multiplexer, and seems to improve timing slightly on the A7-100. Since SPR values are written in stage 3 and read in stage 2, an mfspr immediately following an mtspr to the same SPR won't give the correct value. To avoid this, we make mtspr to the load/store SPRs single issue in decode1. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This commit is contained in:
Paul Mackerras
parent
af814a0d5e
commit
047be5c0c3
@ -681,6 +681,10 @@ begin
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when SPR_DAR | SPR_DSISR | SPR_PID | SPR_PTCR =>
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vi.override_decode.unit := LDST;
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vi.override_unit := '1';
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-- make mtspr to loadstore SPRs single-issue
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if f_in.insn(8) = '1' then
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vi.force_single := '1';
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end if;
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when others =>
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end case;
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end if;
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114
loadstore1.vhdl
114
loadstore1.vhdl
@ -90,7 +90,8 @@ architecture behave of loadstore1 is
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virt_mode : std_ulogic;
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priv_mode : std_ulogic;
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load_sp : std_ulogic;
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sprn : std_ulogic_vector(9 downto 0);
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sprsel : std_ulogic_vector(1 downto 0);
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ric : std_ulogic_vector(1 downto 0);
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is_slbia : std_ulogic;
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align_intr : std_ulogic;
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dword_index : std_ulogic;
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@ -109,7 +110,7 @@ architecture behave of loadstore1 is
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xerc => xerc_init, reserve => '0',
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atomic => '0', atomic_last => '0', rc => '0', nc => '0',
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virt_mode => '0', priv_mode => '0', load_sp => '0',
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sprn => 10x"0", is_slbia => '0', align_intr => '0',
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sprsel => "00", ric => "00", is_slbia => '0', align_intr => '0',
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dword_index => '0', two_dwords => '0', incomplete => '0');
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type reg_stage1_t is record
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@ -130,7 +131,8 @@ architecture behave of loadstore1 is
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wr_sel : std_ulogic_vector(1 downto 0);
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addr0 : std_ulogic_vector(63 downto 0);
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sprsel : std_ulogic_vector(1 downto 0);
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dbg_spr_rd : std_ulogic;
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dbg_spr : std_ulogic_vector(63 downto 0);
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dbg_spr_ack: std_ulogic;
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end record;
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type reg_stage3_t is record
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@ -154,8 +156,6 @@ architecture behave of loadstore1 is
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intr_vec : integer range 0 to 16#fff#;
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srr1 : std_ulogic_vector(15 downto 0);
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events : Loadstore1EventType;
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dbg_spr : std_ulogic_vector(63 downto 0);
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dbg_spr_ack : std_ulogic;
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end record;
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signal req_in : request_t;
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@ -287,7 +287,8 @@ begin
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r1.req.instr_fault <= '0';
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r1.req.load <= '0';
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r1.req.priv_mode <= '0';
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r1.req.sprn <= (others => '0');
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r1.req.sprsel <= "00";
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r1.req.ric <= "00";
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r1.req.xerc <= xerc_init;
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r2.req.valid <= '0';
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@ -297,7 +298,8 @@ begin
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r2.req.instr_fault <= '0';
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r2.req.load <= '0';
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r2.req.priv_mode <= '0';
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r2.req.sprn <= (others => '0');
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r2.req.sprsel <= "00";
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r2.req.ric <= "00";
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r2.req.xerc <= xerc_init;
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r2.wait_dc <= '0';
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@ -418,7 +420,14 @@ begin
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v.nc := l_in.ci;
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v.virt_mode := l_in.virt_mode;
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v.priv_mode := l_in.priv_mode;
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v.sprn := sprn;
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v.ric := l_in.insn(19 downto 18);
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if sprn(1) = '1' then
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-- DSISR and DAR
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v.sprsel := '1' & sprn(0);
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else
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-- PID and PTCR
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v.sprsel := '0' & sprn(8);
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end if;
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lsu_sum := std_ulogic_vector(unsigned(l_in.addr1) + unsigned(l_in.addr2));
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@ -494,7 +503,7 @@ begin
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v.read_spr := '1';
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when OP_MTSPR =>
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v.write_spr := '1';
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v.mmu_op := sprn(8) or sprn(5);
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v.mmu_op := not sprn(1);
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when OP_FETCH_FAILED =>
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-- send it to the MMU to do the radix walk
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v.instr_fault := '1';
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@ -605,6 +614,9 @@ begin
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variable idx : unsigned(2 downto 0);
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variable byte_offset : unsigned(2 downto 0);
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variable interrupt : std_ulogic;
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variable dbg_spr_rd : std_ulogic;
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variable sprsel : std_ulogic_vector(1 downto 0);
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variable sprval : std_ulogic_vector(63 downto 0);
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begin
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v := r2;
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@ -617,6 +629,28 @@ begin
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store_data(i * 8 + 7 downto i * 8) <= r1.req.store_data(j + 7 downto j);
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end loop;
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dbg_spr_rd := dbg_spr_req and not (r1.req.valid and r1.req.read_spr);
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if dbg_spr_rd = '0' then
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sprsel := r1.req.sprsel;
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else
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sprsel := dbg_spr_addr;
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end if;
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if sprsel(1) = '1' then
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if sprsel(0) = '0' then
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sprval := x"00000000" & r3.dsisr;
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else
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sprval := r3.dar;
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end if;
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else
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sprval := m_in.sprval;
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end if;
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if dbg_spr_req = '0' then
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v.dbg_spr_ack := '0';
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elsif dbg_spr_rd = '1' and r2.dbg_spr_ack = '0' then
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v.dbg_spr := sprval;
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v.dbg_spr_ack := '1';
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end if;
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if (dc_stall or d_in.error or r2.busy or l_in.e2stall) = '0' then
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if r1.req.valid = '0' or r1.issued = '1' or r1.req.dc_req = '0' then
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v.req := r1.req;
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@ -627,14 +661,15 @@ begin
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v.wait_mmu := r1.req.valid and r1.req.mmu_op;
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v.busy := r1.req.valid and r1.req.mmu_op;
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v.one_cycle := r1.req.valid and not (r1.req.dc_req or r1.req.mmu_op);
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if r1.req.read_spr = '1' then
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if r1.req.do_update = '1' or r1.req.store = '1' or r1.req.read_spr = '1' then
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v.wr_sel := "00";
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elsif r1.req.do_update = '1' or r1.req.store = '1' then
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v.wr_sel := "01";
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elsif r1.req.load_sp = '1' then
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v.wr_sel := "10";
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v.wr_sel := "01";
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else
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v.wr_sel := "11";
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v.wr_sel := "10";
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end if;
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if r1.req.read_spr = '1' then
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v.addr0 := sprval;
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end if;
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-- Work out load formatter controls for next cycle
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@ -674,21 +709,11 @@ begin
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v.busy := '1';
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end if;
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v.dbg_spr_rd := dbg_spr_req and not (v.req.valid and v.req.read_spr);
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if v.dbg_spr_rd = '0' then
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v.sprsel(1) := v.req.sprn(1);
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if v.req.sprn(1) = '1' then
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-- DSISR and DAR
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v.sprsel(0) := v.req.sprn(0);
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else
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-- PID and PTCR
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v.sprsel(0) := v.req.sprn(8);
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end if;
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else
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v.sprsel := dbg_spr_addr;
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end if;
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r2in <= v;
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-- SPR values for core_debug
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dbg_spr_data <= r2.dbg_spr;
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dbg_spr_ack <= r2.dbg_spr_ack;
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end process;
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-- Processing done in the third cycle of a load/store instruction.
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@ -787,22 +812,6 @@ begin
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v.load_data := data_permuted;
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end if;
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-- SPR mux
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if r2.sprsel(1) = '1' then
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if r2.sprsel(0) = '0' then
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sprval := x"00000000" & r3.dsisr;
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else
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sprval := r3.dar;
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end if;
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else
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sprval := m_in.sprval;
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end if;
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if dbg_spr_req = '0' then
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v.dbg_spr_ack := '0';
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elsif r2.dbg_spr_rd = '1' and r3.dbg_spr_ack = '0' then
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v.dbg_spr := sprval;
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v.dbg_spr_ack := '1';
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end if;
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if r2.req.valid = '1' then
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if r2.req.read_spr = '1' then
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@ -819,7 +828,7 @@ begin
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write_enable := '1';
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end if;
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if r2.req.write_spr = '1' and r2.req.mmu_op = '0' then
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if r2.req.sprn(0) = '0' then
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if r2.req.sprsel(0) = '0' then
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v.dsisr := r2.req.store_data(31 downto 0);
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else
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v.dar := r2.req.store_data;
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@ -917,12 +926,9 @@ begin
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case r2.wr_sel is
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when "00" =>
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-- mfspr result
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write_data := sprval;
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when "01" =>
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-- update reg
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write_data := r2.addr0;
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when "10" =>
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when "01" =>
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-- lfs result
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write_data := load_dp_data;
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when others =>
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@ -969,10 +975,10 @@ begin
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m_out.load <= r2.req.load;
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m_out.priv <= r2.req.priv_mode;
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m_out.tlbie <= r2.req.tlbie;
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m_out.ric <= r2.req.sprn(3 downto 2);
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m_out.ric <= r2.req.ric;
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m_out.mtspr <= mmu_mtspr;
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m_out.sprnf <= r2.sprsel(0);
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m_out.sprnt <= r2.req.sprn(8);
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m_out.sprnf <= r1.req.sprsel(0);
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m_out.sprnt <= r2.req.sprsel(0);
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m_out.addr <= r2.req.addr;
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m_out.slbia <= r2.req.is_slbia;
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m_out.rs <= r2.req.store_data;
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@ -998,10 +1004,6 @@ begin
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flush <= exception;
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-- SPR values for core_debug
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dbg_spr_data <= r3.dbg_spr;
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dbg_spr_ack <= r3.dbg_spr_ack;
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-- Update registers
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r3in <= v;
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