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mirror of https://github.com/antonblanchard/microwatt.git synced 2026-05-04 23:35:58 +00:00

Implement hrfid and make MSR[HV] always 1

Implementations without hypervisor/LPAR support are permitted by the
architecture, but should have MSR[HV] forced to be 1 at all times, not
0, and should implement various instructions and registers that are
only accessible in hypervisor mode.

This commit implements MSR[HV] as a constant 1 bit and adds the hrfid
instruction, which behaves exactly the same as rfid except that it
reads HSRR0/1 instead of SRR0/1.  We already have HSRR0/1 and HSPRG0/1
implemented.

When HV=1, Linux expects external interrupts to arrive as hypervisor
interrupts, so this adds support for hypervisor interrupts (i.e.,
those that set HSRR0/1) and makes the external interrupt be a
hypervisor interrupt.  (If we had an LPCR register, the LPES bit would
control this, but we don't.)  The xics test is updated to read HSRR0/1
after an external interrupt.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This commit is contained in:
Paul Mackerras
2023-08-18 19:29:10 +10:00
parent 6ef9395f10
commit 12a3d76217
11 changed files with 61 additions and 32 deletions

View File

@@ -7,6 +7,7 @@
#define MSR_LE 0x1
#define MSR_DR 0x10
#define MSR_IR 0x20
#define MSR_HV 0x1000000000000000ul
#define MSR_SF 0x8000000000000000ul
#define DSISR 18
@@ -103,7 +104,7 @@ long int prefix_test_2(void)
return 1;
if (mfspr(SRR0) != (unsigned long)&test_paddi_mis + 8)
return 2;
if (mfspr(SRR1) != (MSR_SF | MSR_LE | (1ul << (63 - 35)) | (1ul << (63 - 34))))
if (mfspr(SRR1) != (MSR_SF | MSR_HV | MSR_LE | (1ul << (63 - 35)) | (1ul << (63 - 34))))
return 3;
ret = trapit((long)&x, test_plfd);
@@ -111,7 +112,7 @@ long int prefix_test_2(void)
return ret;
if (mfspr(SRR0) != (unsigned long)&test_plfd + 8)
return 6;
if (mfspr(SRR1) != (MSR_SF | MSR_LE | (1ul << (63 - 34))))
if (mfspr(SRR1) != (MSR_SF | MSR_HV | MSR_LE | (1ul << (63 - 34))))
return 7;
return 0;
}