mirror of
https://github.com/antonblanchard/microwatt.git
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Merge pull request #324 from paulusmack/master
Performance and timing improvements
This commit is contained in:
Michael Neuling
GitHub
commit
2224b28c2c
@ -196,6 +196,7 @@ package common is
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stop_mark: std_ulogic;
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sequential: std_ulogic;
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predicted : std_ulogic;
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pred_ntaken : std_ulogic;
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nia: std_ulogic_vector(63 downto 0);
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end record;
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@ -207,6 +208,7 @@ package common is
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insn: std_ulogic_vector(31 downto 0);
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big_endian: std_ulogic;
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next_predicted: std_ulogic;
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next_pred_ntaken: std_ulogic;
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end record;
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type IcacheEventType is record
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@ -740,6 +740,8 @@ begin
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bv.br_offset := br_offset;
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if f_in.next_predicted = '1' then
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v.br_pred := '1';
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elsif f_in.next_pred_ntaken = '1' then
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v.br_pred := '0';
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end if;
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bv.predict := v.br_pred and f_in.valid and not flush_in and not busy_out and not f_in.next_predicted;
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-- after a clock edge...
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28
fetch1.vhdl
28
fetch1.vhdl
@ -40,7 +40,8 @@ architecture behaviour of fetch1 is
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type reg_internal_t is record
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mode_32bit: std_ulogic;
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rd_is_niap4: std_ulogic;
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predicted: std_ulogic;
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predicted_taken: std_ulogic;
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pred_not_taken: std_ulogic;
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predicted_nia: std_ulogic_vector(63 downto 0);
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end record;
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signal r, r_next : Fetch1ToIcacheType;
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@ -52,7 +53,7 @@ architecture behaviour of fetch1 is
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constant BTC_TAG_BITS : integer := 62 - BTC_ADDR_BITS;
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constant BTC_TARGET_BITS : integer := 62;
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constant BTC_SIZE : integer := 2 ** BTC_ADDR_BITS;
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constant BTC_WIDTH : integer := BTC_TAG_BITS + BTC_TARGET_BITS;
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constant BTC_WIDTH : integer := BTC_TAG_BITS + BTC_TARGET_BITS + 1;
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type btc_mem_type is array (0 to BTC_SIZE - 1) of std_ulogic_vector(BTC_WIDTH - 1 downto 0);
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signal btc_rd_data : std_ulogic_vector(BTC_WIDTH - 1 downto 0) := (others => '0');
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@ -83,8 +84,10 @@ begin
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end if;
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if advance_nia = '1' then
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r.predicted <= r_next.predicted;
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r.pred_ntaken <= r_next.pred_ntaken;
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r.nia <= r_next.nia;
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r_int.predicted <= r_next_int.predicted;
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r_int.predicted_taken <= r_next_int.predicted_taken;
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r_int.pred_not_taken <= r_next_int.pred_not_taken;
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r_int.predicted_nia <= r_next_int.predicted_nia;
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r_int.rd_is_niap4 <= r_next.sequential;
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end if;
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@ -107,13 +110,12 @@ begin
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signal btc_wr : std_ulogic;
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signal btc_wr_data : std_ulogic_vector(BTC_WIDTH - 1 downto 0);
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signal btc_wr_addr : std_ulogic_vector(BTC_ADDR_BITS - 1 downto 0);
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signal btc_wr_v : std_ulogic;
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begin
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btc_wr_data <= w_in.br_nia(63 downto BTC_ADDR_BITS + 2) &
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btc_wr_data <= w_in.br_taken &
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w_in.br_nia(63 downto BTC_ADDR_BITS + 2) &
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w_in.redirect_nia(63 downto 2);
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btc_wr_addr <= w_in.br_nia(BTC_ADDR_BITS + 1 downto 2);
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btc_wr <= w_in.br_last;
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btc_wr_v <= w_in.br_taken;
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btc_ram : process(clk)
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variable raddr : unsigned(BTC_ADDR_BITS - 1 downto 0);
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@ -131,7 +133,7 @@ begin
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if inval_btc = '1' or rst = '1' then
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btc_valids <= (others => '0');
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elsif btc_wr = '1' then
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btc_valids(to_integer(unsigned(btc_wr_addr))) <= btc_wr_v;
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btc_valids(to_integer(unsigned(btc_wr_addr))) <= '1';
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end if;
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end if;
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end process;
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@ -145,7 +147,9 @@ begin
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v_int := r_int;
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v.sequential := '0';
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v.predicted := '0';
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v_int.predicted := '0';
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v.pred_ntaken := '0';
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v_int.predicted_taken := '0';
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v_int.pred_not_taken := '0';
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if rst = '1' then
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if alt_reset_in = '1' then
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@ -172,19 +176,21 @@ begin
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if r_int.mode_32bit = '1' then
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v.nia(63 downto 32) := (others => '0');
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end if;
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elsif r_int.predicted = '1' then
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elsif r_int.predicted_taken = '1' then
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v.nia := r_int.predicted_nia;
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v.predicted := '1';
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else
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v.sequential := '1';
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v.pred_ntaken := r_int.pred_not_taken;
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v.nia := std_ulogic_vector(unsigned(r.nia) + 4);
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if r_int.mode_32bit = '1' then
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v.nia(63 downto 32) := x"00000000";
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end if;
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if btc_rd_valid = '1' and r_int.rd_is_niap4 = '1' and
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btc_rd_data(BTC_WIDTH - 1 downto BTC_TARGET_BITS)
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btc_rd_data(BTC_WIDTH - 2 downto BTC_TARGET_BITS)
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= v.nia(BTC_TAG_BITS + BTC_ADDR_BITS + 1 downto BTC_ADDR_BITS + 2) then
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v_int.predicted := '1';
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v_int.predicted_taken := btc_rd_data(BTC_WIDTH - 1);
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v_int.pred_not_taken := not btc_rd_data(BTC_WIDTH - 1);
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end if;
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end if;
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v_int.predicted_nia := btc_rd_data(BTC_TARGET_BITS - 1 downto 0) & "00";
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@ -577,6 +577,7 @@ begin
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i_out.fetch_failed <= r.fetch_failed;
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i_out.big_endian <= r.big_endian;
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i_out.next_predicted <= i_in.predicted;
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i_out.next_pred_ntaken <= i_in.pred_ntaken;
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-- Stall fetch1 if we have a miss on cache or TLB or a protection fault
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stall_out <= not (is_hit and access_ok);
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@ -24,7 +24,6 @@ architecture behaviour of multiply is
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signal m11_pc, m12_pc, m13_pc : std_ulogic_vector(47 downto 0);
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signal m20_p, m21_p, m22_p, m23_p : std_ulogic_vector(47 downto 0);
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signal s0_pc, s1_pc : std_ulogic_vector(47 downto 0);
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signal product_lo : std_ulogic_vector(31 downto 0);
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signal product : std_ulogic_vector(127 downto 0);
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signal addend : std_ulogic_vector(127 downto 0);
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signal s0_carry, p0_carry : std_ulogic_vector(3 downto 0);
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@ -33,7 +32,7 @@ architecture behaviour of multiply is
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signal p1_pat, p1_patb : std_ulogic;
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signal req_32bit, r32_1 : std_ulogic;
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signal req_not, rnot_1 : std_ulogic;
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signal rnot_1 : std_ulogic;
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signal valid_1 : std_ulogic;
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signal overflow, ovf_in : std_ulogic;
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@ -49,9 +48,11 @@ begin
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BREG => 0,
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CARRYINREG => 0,
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CARRYINSELREG => 0,
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CREG => 0,
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INMODEREG => 0,
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MREG => 0,
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OPMODEREG => 0,
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PREG => 0
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PREG => 1
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)
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port map (
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A => "0000000" & m_in.data1(22 downto 0),
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@ -69,13 +70,13 @@ begin
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CEALUMODE => '0',
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CEB1 => '0',
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CEB2 => '0',
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CEC => '1',
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CEC => '0',
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CECARRYIN => '0',
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CECTRL => '0',
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CED => '0',
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CEINMODE => '0',
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CEM => m_in.valid,
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CEP => '0',
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CEM => '0',
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CEP => m_in.valid,
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CLK => clk,
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D => (others => '0'),
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INMODE => "00000",
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@ -160,9 +161,11 @@ begin
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BREG => 0,
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CARRYINREG => 0,
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CARRYINSELREG => 0,
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CREG => 0,
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INMODEREG => 0,
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MREG => 0,
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OPMODEREG => 0,
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PREG => 0
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PREG => 1
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)
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port map (
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A => "0000000" & m_in.data1(22 downto 0),
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@ -180,13 +183,13 @@ begin
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CEALUMODE => '0',
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CEB1 => '0',
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CEB2 => '0',
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CEC => '1',
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CEC => '0',
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CECARRYIN => '0',
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CECTRL => '0',
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CED => '0',
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CEINMODE => '0',
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CEM => m_in.valid,
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CEP => '0',
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CEM => '0',
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CEP => m_in.valid,
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CLK => clk,
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D => (others => '0'),
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INMODE => "00000",
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@ -215,9 +218,11 @@ begin
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BREG => 0,
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CARRYINREG => 0,
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CARRYINSELREG => 0,
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CREG => 0,
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INMODEREG => 0,
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MREG => 0,
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OPMODEREG => 0,
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PREG => 0
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PREG => 1
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)
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port map (
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A => "0000000" & m_in.data1(22 downto 0),
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@ -235,13 +240,13 @@ begin
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CEALUMODE => '0',
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CEB1 => '0',
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CEB2 => '0',
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CEC => '1',
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CEC => '0',
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CECARRYIN => '0',
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CECTRL => '0',
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CED => '0',
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CEINMODE => '0',
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CEM => m_in.valid,
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CEP => '0',
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CEM => '0',
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CEP => m_in.valid,
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CLK => clk,
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D => (others => '0'),
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INMODE => "00000",
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@ -709,18 +714,18 @@ begin
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s0: DSP48E1
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generic map (
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ACASCREG => 1,
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ACASCREG => 0,
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ALUMODEREG => 0,
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AREG => 1,
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BCASCREG => 1,
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BREG => 1,
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AREG => 0,
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BCASCREG => 0,
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BREG => 0,
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CARRYINREG => 0,
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CARRYINSELREG => 0,
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CREG => 1,
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CREG => 0,
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INMODEREG => 0,
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MREG => 0,
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OPMODEREG => 0,
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PREG => 0,
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PREG => 1,
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USE_MULT => "none"
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)
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port map (
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@ -735,18 +740,18 @@ begin
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CARRYINSEL => "000",
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CARRYOUT => s0_carry,
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CEA1 => '0',
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CEA2 => valid_1,
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CEA2 => '0',
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CEAD => '0',
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CEALUMODE => '0',
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CEB1 => '0',
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CEB2 => valid_1,
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CEC => valid_1,
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CEB2 => '0',
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CEC => '0',
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CECARRYIN => '0',
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CECTRL => '0',
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CED => '0',
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CEINMODE => '0',
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CEM => '0',
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CEP => '0',
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CEP => valid_1,
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CLK => clk,
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D => (others => '0'),
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INMODE => "00000",
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@ -953,8 +958,6 @@ begin
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RSTP => '0'
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);
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product(31 downto 0) <= product_lo xor (31 downto 0 => req_not);
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mult_out: process(all)
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variable ov : std_ulogic;
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begin
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@ -974,12 +977,15 @@ begin
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process(clk)
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begin
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if rising_edge(clk) then
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product_lo <= m10_p(8 downto 0) & m01_p(5 downto 0) & m00_p(16 downto 0);
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if rnot_1 = '0' then
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product(31 downto 0) <= m10_p(8 downto 0) & m01_p(5 downto 0) & m00_p(16 downto 0);
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else
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product(31 downto 0) <= not (m10_p(8 downto 0) & m01_p(5 downto 0) & m00_p(16 downto 0));
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end if;
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m_out.valid <= valid_1;
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valid_1 <= m_in.valid;
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req_32bit <= r32_1;
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r32_1 <= m_in.is_32bit;
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req_not <= rnot_1;
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rnot_1 <= m_in.not_result;
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overflow <= ovf_in;
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end if;
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