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Merge pull request #390 from shenki/fix-whide-warnings
Fix -Whide warnings
This commit is contained in:
Michael Neuling
GitHub
commit
2562053af3
102
fpu.vhdl
102
fpu.vhdl
@ -389,7 +389,7 @@ architecture behaviour of fpu is
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return std_ulogic_vector is
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variable s1 : std_ulogic_vector(94 downto 0);
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variable s2 : std_ulogic_vector(70 downto 0);
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variable result : std_ulogic_vector(63 downto 0);
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variable shift_result : std_ulogic_vector(63 downto 0);
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begin
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case shift(6 downto 5) is
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when "00" =>
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@ -413,23 +413,23 @@ architecture behaviour of fpu is
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end case;
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case shift(2 downto 0) is
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when "000" =>
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result := s2(70 downto 7);
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shift_result := s2(70 downto 7);
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when "001" =>
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result := s2(69 downto 6);
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shift_result := s2(69 downto 6);
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when "010" =>
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result := s2(68 downto 5);
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shift_result := s2(68 downto 5);
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when "011" =>
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result := s2(67 downto 4);
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shift_result := s2(67 downto 4);
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when "100" =>
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result := s2(66 downto 3);
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shift_result := s2(66 downto 3);
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when "101" =>
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result := s2(65 downto 2);
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shift_result := s2(65 downto 2);
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when "110" =>
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result := s2(64 downto 1);
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shift_result := s2(64 downto 1);
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when others =>
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result := s2(63 downto 0);
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shift_result := s2(63 downto 0);
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end case;
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return result;
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return shift_result;
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end;
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-- Generate a mask with 0-bits on the left and 1-bits on the right which
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@ -437,105 +437,105 @@ architecture behaviour of fpu is
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-- parameter is the bottom 6 bits of a negative shift count,
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-- indicating a right shift.
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function right_mask(shift: unsigned(5 downto 0)) return std_ulogic_vector is
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variable result: std_ulogic_vector(63 downto 0);
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variable mask_result: std_ulogic_vector(63 downto 0);
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begin
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result := (others => '0');
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mask_result := (others => '0');
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if is_X(shift) then
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result := (others => 'X');
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return result;
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mask_result := (others => 'X');
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return mask_result;
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end if;
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for i in 0 to 63 loop
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if i >= shift then
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result(63 - i) := '1';
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mask_result(63 - i) := '1';
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end if;
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end loop;
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return result;
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return mask_result;
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end;
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-- Split a DP floating-point number into components and work out its class.
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-- If is_int = 1, the input is considered an integer
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function decode_dp(fpr: std_ulogic_vector(63 downto 0); is_int: std_ulogic;
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is_32bint: std_ulogic; is_signed: std_ulogic) return fpu_reg_type is
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variable r : fpu_reg_type;
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variable reg : fpu_reg_type;
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variable exp_nz : std_ulogic;
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variable exp_ao : std_ulogic;
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variable frac_nz : std_ulogic;
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variable low_nz : std_ulogic;
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variable cls : std_ulogic_vector(2 downto 0);
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begin
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r.negative := fpr(63);
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reg.negative := fpr(63);
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exp_nz := or (fpr(62 downto 52));
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exp_ao := and (fpr(62 downto 52));
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frac_nz := or (fpr(51 downto 0));
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low_nz := or (fpr(31 downto 0));
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if is_int = '0' then
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r.exponent := signed(resize(unsigned(fpr(62 downto 52)), EXP_BITS)) - to_signed(1023, EXP_BITS);
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reg.exponent := signed(resize(unsigned(fpr(62 downto 52)), EXP_BITS)) - to_signed(1023, EXP_BITS);
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if exp_nz = '0' then
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r.exponent := to_signed(-1022, EXP_BITS);
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reg.exponent := to_signed(-1022, EXP_BITS);
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end if;
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r.mantissa := std_ulogic_vector(shift_left(resize(unsigned(exp_nz & fpr(51 downto 0)), 64),
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UNIT_BIT - 52));
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reg.mantissa := std_ulogic_vector(shift_left(resize(unsigned(exp_nz & fpr(51 downto 0)), 64),
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UNIT_BIT - 52));
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cls := exp_ao & exp_nz & frac_nz;
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case cls is
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when "000" => r.class := ZERO;
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when "001" => r.class := FINITE; -- denormalized
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when "010" => r.class := FINITE;
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when "011" => r.class := FINITE;
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when "110" => r.class := INFINITY;
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when others => r.class := NAN;
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when "000" => reg.class := ZERO;
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when "001" => reg.class := FINITE; -- denormalized
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when "010" => reg.class := FINITE;
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when "011" => reg.class := FINITE;
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when "110" => reg.class := INFINITY;
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when others => reg.class := NAN;
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end case;
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elsif is_32bint = '1' then
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r.negative := fpr(31);
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r.mantissa(31 downto 0) := fpr(31 downto 0);
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r.mantissa(63 downto 32) := (others => (is_signed and fpr(31)));
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r.exponent := (others => '0');
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reg.negative := fpr(31);
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reg.mantissa(31 downto 0) := fpr(31 downto 0);
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reg.mantissa(63 downto 32) := (others => (is_signed and fpr(31)));
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reg.exponent := (others => '0');
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if low_nz = '1' then
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r.class := FINITE;
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reg.class := FINITE;
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else
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r.class := ZERO;
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reg.class := ZERO;
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end if;
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else
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r.mantissa := fpr;
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r.exponent := (others => '0');
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reg.mantissa := fpr;
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reg.exponent := (others => '0');
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if (fpr(63) or exp_nz or frac_nz) = '1' then
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r.class := FINITE;
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reg.class := FINITE;
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else
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r.class := ZERO;
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reg.class := ZERO;
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end if;
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end if;
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return r;
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return reg;
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end;
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-- Construct a DP floating-point result from components
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function pack_dp(sign: std_ulogic; class: fp_number_class; exp: signed(EXP_BITS-1 downto 0);
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mantissa: std_ulogic_vector; single_prec: std_ulogic; quieten_nan: std_ulogic)
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return std_ulogic_vector is
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variable result : std_ulogic_vector(63 downto 0);
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variable dp_result : std_ulogic_vector(63 downto 0);
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begin
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result := (others => '0');
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result(63) := sign;
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dp_result := (others => '0');
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dp_result(63) := sign;
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case class is
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when ZERO =>
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when FINITE =>
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if mantissa(UNIT_BIT) = '1' then
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-- normalized number
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result(62 downto 52) := std_ulogic_vector(resize(exp, 11) + 1023);
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dp_result(62 downto 52) := std_ulogic_vector(resize(exp, 11) + 1023);
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end if;
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result(51 downto 29) := mantissa(UNIT_BIT - 1 downto SP_LSB);
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dp_result(51 downto 29) := mantissa(UNIT_BIT - 1 downto SP_LSB);
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if single_prec = '0' then
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result(28 downto 0) := mantissa(SP_LSB - 1 downto DP_LSB);
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dp_result(28 downto 0) := mantissa(SP_LSB - 1 downto DP_LSB);
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end if;
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when INFINITY =>
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result(62 downto 52) := "11111111111";
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dp_result(62 downto 52) := "11111111111";
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when NAN =>
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result(62 downto 52) := "11111111111";
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result(51) := quieten_nan or mantissa(QNAN_BIT);
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result(50 downto 29) := mantissa(QNAN_BIT - 1 downto SP_LSB);
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dp_result(62 downto 52) := "11111111111";
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dp_result(51) := quieten_nan or mantissa(QNAN_BIT);
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dp_result(50 downto 29) := mantissa(QNAN_BIT - 1 downto SP_LSB);
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if single_prec = '0' then
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result(28 downto 0) := mantissa(SP_LSB - 1 downto DP_LSB);
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dp_result(28 downto 0) := mantissa(SP_LSB - 1 downto DP_LSB);
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end if;
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end case;
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return result;
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return dp_result;
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end;
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-- Determine whether to increment when rounding
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2
soc.vhdl
2
soc.vhdl
@ -841,7 +841,7 @@ begin
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--
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-- Always 16550 if it exists
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--
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uart1: if HAS_UART1 generate
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uart1_16550: if HAS_UART1 generate
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signal irq_l : std_ulogic;
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begin
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uart1: uart_top
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14
xics.vhdl
14
xics.vhdl
@ -80,14 +80,14 @@ begin
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variable v : reg_internal_t;
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variable xirr_accept_rd : std_ulogic;
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function bswap(v : in std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
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variable r : std_ulogic_vector(31 downto 0);
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function bswap(vec : in std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
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variable rout : std_ulogic_vector(31 downto 0);
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begin
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r( 7 downto 0) := v(31 downto 24);
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r(15 downto 8) := v(23 downto 16);
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r(23 downto 16) := v(15 downto 8);
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r(31 downto 24) := v( 7 downto 0);
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return r;
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rout( 7 downto 0) := vec(31 downto 24);
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rout(15 downto 8) := vec(23 downto 16);
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rout(23 downto 16) := vec(15 downto 8);
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rout(31 downto 24) := vec( 7 downto 0);
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return rout;
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end function;
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variable be_in : std_ulogic_vector(31 downto 0);
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