dcache: Remove reset on read port of cache tag RAM

The reset was added originally to reduce metavalue warnings in
simulation, is not necessary for correct operation, and showed up as a
critical path in synthesis for the Xilinx Artix-7.  Remove it when
doing synthesis; for simulation we set the value read to X rather than
0 in order to catch any use of the previously reset value.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

core.vhdl

@@ -468,6 +468,7 @@ begin
 
     dcache_0: entity work.dcache
         generic map(
+            SIM => SIM,
             LINE_SIZE => 64,
             NUM_LINES => DCACHE_NUM_LINES,
             NUM_WAYS => DCACHE_NUM_WAYS,

dcache.vhdl

@@ -14,6 +14,7 @@ use work.wishbone_types.all;
 
 entity dcache is
     generic (
+        SIM : boolean := false;
         -- Line size in bytes
         LINE_SIZE : positive := 64;
         -- Number of lines in a set
@@ -922,10 +923,10 @@ begin
                 index := get_index(d_in.addr);
                 valid := d_in.valid;
             end if;
-            if valid = '1' then
+            if valid = '1' or not SIM then
                 cache_tag_set <= cache_tags(to_integer(index));
             else
-                cache_tag_set <= (others => '0');
+                cache_tag_set <= (others => 'X');
             end if;
         end if;
     end process;