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MMU: Implement reading of the process table

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This adds the PID register and repurposes SPR 720 as the PRTBL
register, which points to the base of the process table.  There
doesn't seem to be any point to implementing the partition table given
that we don't have hypervisor mode.

The MMU caches entry 0 of the process table internally (in pgtbl3)
plus the entry indexed by the value in the PID register (pgtbl0).
Both caches are invalidated by a tlbie[l] with RIC=2 or by a move to
PRTBL.  The pgtbl0 cache is invalidated by a move to PID.  The dTLB
and iTLB are cleared by a move to either PRTBL or PID.

Which of the two page table root pointers is used (pgtbl0 or pgtbl3)
depends on the MSB of the address being translated.  Since the segment
checking ensures that address(63) = address(62), this is sufficient to
map quadrants 0 and 3.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This commit is contained in:
Paul Mackerras
2020-04-24 10:58:56 +10:00
parent f3c6119cf6
commit 2843c99a71
8 changed files with 134 additions and 27 deletions
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11
tests/mmu/mmu.c
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@@ -21,6 +21,8 @@ static inline void do_tlbie(unsigned long rb, unsigned long rs)
#define DAR 19
#define SRR0 26
#define SRR1 27
#define PID 48
#define PRTBL 720
static inline unsigned long mfspr(int sprnum)
{
@@ -110,15 +112,20 @@ void zero_memory(void *ptr, unsigned long nbytes)
* 8kB PGD level pointing to 4kB PTE pages.
*/
unsigned long *pgdir = (unsigned long *) 0x10000;
unsigned long free_ptr = 0x12000;
unsigned long *proc_tbl = (unsigned long *) 0x12000;
unsigned long free_ptr = 0x13000;
void *eas_mapped[4];
int neas_mapped;
void init_mmu(void)
{
/* set up process table */
zero_memory(proc_tbl, 512 * sizeof(unsigned long));
mtspr(PRTBL, (unsigned long)proc_tbl);
mtspr(PID, 1);
zero_memory(pgdir, 1024 * sizeof(unsigned long));
/* RTS = 0 (2GB address space), RPDS = 10 (1024-entry top level) */
mtspr(720, (unsigned long) pgdir | 10);
store_pte(&proc_tbl[2 * 1], (unsigned long) pgdir | 10);
do_tlbie(0xc00, 0); /* invalidate all TLB entries */
}