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loadstore1: Further tweaks to improve synthesis with yosys/nextpnr
This reworks the way that the busy and done signals are generated in loadstore in order to work around some problems where yosys/nextpnr are reporting combinatorial loops (not in fact on the current code but on minor variations needed for supporting the FPU). It seems that yosys has problems with the case statement on v.state. This also lifts the maddr and byte_sel generation out of the case statement. The overall result is a slight reduction in resource usage (~30 6-input LUTs on the A7-100). Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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Paul Mackerras
parent
128fe8ac26
commit
2cb1d7671e
@ -44,10 +44,9 @@ architecture behave of loadstore1 is
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type state_t is (IDLE, -- ready for instruction
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SECOND_REQ, -- send 2nd request of unaligned xfer
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ACK_WAIT, -- waiting for ack from dcache
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LD_UPDATE, -- writing rA with computed addr on load
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MMU_LOOKUP, -- waiting for MMU to look up translation
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TLBIE_WAIT, -- waiting for MMU to finish doing a tlbie
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SPR_CMPLT -- complete a mf/tspr operation
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COMPLETE -- extra cycle to complete an operation
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);
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type reg_stage_t is record
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@ -83,6 +82,8 @@ architecture behave of loadstore1 is
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busy : std_ulogic;
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wait_dcache : std_ulogic;
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wait_mmu : std_ulogic;
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do_update : std_ulogic;
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extra_cycle : std_ulogic;
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end record;
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type byte_sel_t is array(0 to 7) of std_ulogic;
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@ -132,8 +133,7 @@ begin
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if rst = '1' then
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r.state <= IDLE;
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r.busy <= '0';
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r.wait_dcache <= '0';
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r.wait_mmu <= '0';
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r.do_update <= '0';
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else
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r <= rin;
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end if;
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@ -172,9 +172,6 @@ begin
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begin
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v := r;
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req := '0';
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byte_sel := (others => '0');
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addr := lsu_sum;
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maddr := l_in.addr2; -- address from RB for tlbie
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v.mfspr := '0';
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mmu_mtspr := '0';
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itlb_fault := '0';
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@ -183,7 +180,9 @@ begin
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mmureq := '0';
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write_enable := '0';
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do_update := '0';
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do_update := r.do_update;
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v.do_update := '0';
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-- load data formatting
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byte_offset := unsigned(r.addr(2 downto 0));
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@ -239,7 +238,8 @@ begin
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-- Busy calculation.
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-- We need to minimize the delay from clock to busy valid because it
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-- gates the start of execution of the next instruction.
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busy := r.busy or (r.wait_dcache and not d_in.valid) or (r.wait_mmu and not m_in.done);
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busy := r.busy and not ((r.wait_dcache and d_in.valid) or (r.wait_mmu and m_in.done));
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v.busy := busy;
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done := '0';
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if r.state /= IDLE and busy = '0' then
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@ -247,12 +247,19 @@ begin
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end if;
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exception := '0';
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if r.dwords_done = '1' or r.state = SECOND_REQ then
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maddr := next_addr;
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byte_sel := r.second_bytes;
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else
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maddr := r.addr;
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byte_sel := r.first_bytes;
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end if;
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addr := maddr;
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case r.state is
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when IDLE =>
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when SECOND_REQ =>
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addr := next_addr;
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byte_sel := r.second_bytes;
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req := '1';
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v.state := ACK_WAIT;
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v.last_dword := '0';
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@ -261,11 +268,6 @@ begin
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if d_in.error = '1' then
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-- dcache will discard the second request if it
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-- gets an error on the 1st of two requests
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if r.dwords_done = '1' then
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maddr := next_addr;
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else
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maddr := r.addr;
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end if;
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if d_in.cache_paradox = '1' then
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-- signal an interrupt straight away
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exception := '1';
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@ -289,24 +291,22 @@ begin
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end if;
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else
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write_enable := r.load;
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if r.load = '1' and r.update = '1' then
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if r.extra_cycle = '1' then
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-- loads with rA update need an extra cycle
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v.state := LD_UPDATE;
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v.state := COMPLETE;
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v.do_update := r.update;
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else
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-- stores write back rA update in this cycle
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do_update := r.update;
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end if;
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v.busy := '0';
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end if;
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end if;
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-- r.wait_dcache gets set one cycle after we come into ACK_WAIT state,
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-- which is OK because the dcache always takes at least two cycles.
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v.wait_dcache := r.last_dword and not r.extra_cycle;
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when MMU_LOOKUP =>
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if r.dwords_done = '1' then
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addr := next_addr;
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byte_sel := r.second_bytes;
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else
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addr := r.addr;
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byte_sel := r.first_bytes;
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end if;
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if m_in.done = '1' then
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if r.instr_fault = '0' then
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-- retry the request now that the MMU has installed a TLB entry
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@ -329,15 +329,13 @@ begin
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when TLBIE_WAIT =>
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when LD_UPDATE =>
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do_update := '1';
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when SPR_CMPLT =>
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when COMPLETE =>
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end case;
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if done = '1' or exception = '1' then
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v.state := IDLE;
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v.busy := '0';
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end if;
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-- Note that l_in.valid is gated with busy inside execute1
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@ -361,6 +359,13 @@ begin
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v.nc := l_in.ci;
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v.virt_mode := l_in.virt_mode;
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v.priv_mode := l_in.priv_mode;
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v.wait_dcache := '0';
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v.wait_mmu := '0';
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v.do_update := '0';
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v.extra_cycle := '0';
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addr := lsu_sum;
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maddr := l_in.addr2; -- address from RB for tlbie
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-- XXX Temporary hack. Mark the op as non-cachable if the address
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-- is the form 0xc------- for a real-mode access.
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@ -392,6 +397,8 @@ begin
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when OP_LOAD =>
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req := '1';
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v.load := '1';
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-- Allow an extra cycle for RA update on loads
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v.extra_cycle := l_in.update;
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when OP_DCBZ =>
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req := '1';
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v.dcbz := '1';
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@ -399,6 +406,7 @@ begin
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mmureq := '1';
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v.tlbie := '1';
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v.state := TLBIE_WAIT;
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v.wait_mmu := '1';
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when OP_MFSPR =>
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v.mfspr := '1';
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-- partial decode on SPR number should be adequate given
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@ -413,7 +421,7 @@ begin
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-- reading one of the SPRs in the MMU
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v.sprval := m_in.sprval;
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end if;
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v.state := SPR_CMPLT;
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v.state := COMPLETE;
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when OP_MTSPR =>
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if sprn(9) = '0' and sprn(5) = '0' then
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if sprn(0) = '0' then
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@ -421,11 +429,12 @@ begin
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else
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v.dar := l_in.data;
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end if;
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v.state := SPR_CMPLT;
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v.state := COMPLETE;
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else
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-- writing one of the SPRs in the MMU
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mmu_mtspr := '1';
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v.state := TLBIE_WAIT;
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v.wait_mmu := '1';
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end if;
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when OP_FETCH_FAILED =>
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-- send it to the MMU to do the radix walk
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@ -433,6 +442,7 @@ begin
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v.instr_fault := '1';
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mmureq := '1';
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v.state := MMU_LOOKUP;
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v.wait_mmu := '1';
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when others =>
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assert false report "unknown op sent to loadstore1";
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end case;
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@ -444,32 +454,9 @@ begin
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v.state := SECOND_REQ;
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end if;
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end if;
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end if;
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-- Work out whether we'll be busy next cycle
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v.busy := '0';
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v.wait_dcache := '0';
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v.wait_mmu := '0';
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case v.state is
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when SECOND_REQ =>
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v.busy := '1';
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when ACK_WAIT =>
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if v.last_dword = '0' or (v.load = '1' and v.update = '1') then
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v.busy := '1';
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else
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v.wait_dcache := '1';
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v.busy := req or mmureq or mmu_mtspr;
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end if;
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when MMU_LOOKUP =>
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if v.instr_fault = '0' then
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v.busy := '1';
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else
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v.wait_mmu := '1';
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end if;
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when TLBIE_WAIT =>
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v.wait_mmu := '1';
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when others =>
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-- not busy next cycle
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end case;
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-- Update outputs to dcache
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d_out.valid <= req;
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