soc: Move timebase back into the core and enable writing to it

Instead of a single global timebase register in the SoC, we now have
a timebase counter in each core; however, now they are only reset by
the soc reset, not the core reset.  Thus they stay in sync even when
some cores are disabled (via the syscon cpu_ctrl register).

This implements mtspr to the TBLW and TBUW SPRs, which write the lower
and upper 32 bits of this core's timebase, respectively.

In order to fulfil the ISA's requirements that (a) some method for
getting the timebases into sync and (b) some method for preventing
userspace from reading the timebase be provided by the platform, this
adds a syscon register TB_CTRL with two read/write bits implemented;
bit 0 freezes all the timebases in the system when set, and bit 1
makes reading the timebase privileged (in all cores).

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

include/microwatt_soc.h

@@ -67,6 +67,9 @@
 #define   SYS_REG_GIT_IS_DIRTY			(1ull << 63)
 #define SYS_REG_CPU_CTRL		0x58
 #define   SYS_REG_CPU_CTRL_ENABLE		0xff
+#define SYS_REG_TB_CTRL			0x60
+#define   SYS_REG_TB_CTRL_FREEZE		0x01
+#define   SYS_REG_TB_CTRL_RD_PROTECT		0x02
 
 /*
  * Register definitions for the potato UART