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Replaced VHDL assert and report with VUnit checking and logging

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The VUnit log package is a SW style logging framework in VHDL and the check package is an assertion library doing its error reporting with VUnit logging.
These testbenches don't use, and do not need, very advanced logging/checking features but the following was possible to improve

- Checking equality in VHDL can be quite tedious with a lot of type conversions and long message strings to explain the data received and what was expected.
  VUnit's check_equal procedure allow comparison between same or similar types and automatically create the error message for you.
- The code has report statements used for testbench progress reporting and debugging. These were replaced with the info and debug procedures.
  info logs are visible by default while debug is not. This means that debug logs don't have to be commented, which they are now, when not used.
  Instead there is a show procedure making debug messages visible. The show procedure has been commented to hide the debug messages but a more elegant
  solution is to control visibility from a generic and then set that generic from the command line. I've left this as a TODO but the run script allow you to
  extend the standard CLI of VUnit to add new options and you can also set generics from the run script.
- VUnit log messages are color coded if color codes are supported by the terminal. It makes it quicker to spot messages of different types when there are many log messages.
  Error messages will always be made visible on the terminal but you must use the -v (verbose) to see other logs.
- Some tests have a lot of "metvalue detected" warning messages from the numeric_std package and these clutter the logs when using the -v option. VUnit has a simulator independent
  option allowing you to suppress those messages. That option has been enabled.

Signed-off-by: Lars Asplund <lars.anders.asplund@gmail.com>
This commit is contained in:
Lars Asplund 2021-06-09 23:50:02 +02:00
parent 0865704e21
commit 478b787c10
6 changed files with 131 additions and 175 deletions
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35
countzero_tb.vhdl
View File

@ -19,8 +19,7 @@ architecture behave of countzero_tb is
constant clk_period: time := 10 ns; constant clk_period: time := 10 ns;
signal rs: std_ulogic_vector(63 downto 0); signal rs: std_ulogic_vector(63 downto 0);
signal is_32bit, count_right: std_ulogic := '0'; signal is_32bit, count_right: std_ulogic := '0';
signal result: std_ulogic_vector(63 downto 0); signal res: std_ulogic_vector(63 downto 0);
signal randno: std_ulogic_vector(63 downto 0);
signal clk: std_ulogic; signal clk: std_ulogic;
begin begin
@ -28,7 +27,7 @@ begin
port map ( port map (
clk => clk, clk => clk,
rs => rs, rs => rs,
result => result, result => res,
count_right => count_right, count_right => count_right,
is_32bit => is_32bit is_32bit => is_32bit
); );
@ -55,21 +54,17 @@ begin
is_32bit <= '0'; is_32bit <= '0';
count_right <= '0'; count_right <= '0';
wait for clk_period; wait for clk_period;
assert result = x"0000000000000040" check_equal(res, 16#40#, result("for cntlzd"));
report "bad cntlzd 0 = " & to_hstring(result);
count_right <= '1'; count_right <= '1';
wait for clk_period; wait for clk_period;
assert result = x"0000000000000040" check_equal(res, 16#40#, result("for cnttzd"));
report "bad cnttzd 0 = " & to_hstring(result);
is_32bit <= '1'; is_32bit <= '1';
count_right <= '0'; count_right <= '0';
wait for clk_period; wait for clk_period;
assert result = x"0000000000000020" check_equal(res, 16#20#, result("for cntlzw"));
report "bad cntlzw 0 = " & to_hstring(result);
count_right <= '1'; count_right <= '1';
wait for clk_period; wait for clk_period;
assert result = x"0000000000000020" check_equal(res, 16#20#, result("for cnttzw"));
report "bad cnttzw 0 = " & to_hstring(result);
elsif run("Test cntlzd/w") then elsif run("Test cntlzd/w") then
count_right <= '0'; count_right <= '0';
@ -80,17 +75,14 @@ begin
rs <= r; rs <= r;
is_32bit <= '0'; is_32bit <= '0';
wait for clk_period; wait for clk_period;
assert to_integer(unsigned(result)) = i check_equal(res, i, result("for cntlzd " & to_hstring(rs)));
report "bad cntlzd " & to_hstring(rs) & " -> " & to_hstring(result);
rs <= r(31 downto 0) & r(63 downto 32); rs <= r(31 downto 0) & r(63 downto 32);
is_32bit <= '1'; is_32bit <= '1';
wait for clk_period; wait for clk_period;
if i < 32 then if i < 32 then
assert to_integer(unsigned(result)) = i check_equal(res, i, result("for cntlzw " & to_hstring(rs)));
report "bad cntlzw " & to_hstring(rs) & " -> " & to_hstring(result);
else else
assert to_integer(unsigned(result)) = 32 check_equal(res, 32, result("for cntlzw " & to_hstring(rs)));
report "bad cntlzw " & to_hstring(rs) & " -> " & to_hstring(result);
end if; end if;
r := '0' & r(63 downto 1); r := '0' & r(63 downto 1);
end loop; end loop;
@ -105,16 +97,13 @@ begin
rs <= r; rs <= r;
is_32bit <= '0'; is_32bit <= '0';
wait for clk_period; wait for clk_period;
assert to_integer(unsigned(result)) = i check_equal(res, i, result("for cnttzd " & to_hstring(rs)));
report "bad cnttzd " & to_hstring(rs) & " -> " & to_hstring(result);
is_32bit <= '1'; is_32bit <= '1';
wait for clk_period; wait for clk_period;
if i < 32 then if i < 32 then
assert to_integer(unsigned(result)) = i check_equal(res, i, result("for cnttzw " & to_hstring(rs)));
report "bad cnttzw " & to_hstring(rs) & " -> " & to_hstring(result);
else else
assert to_integer(unsigned(result)) = 32 check_equal(res, 32, result("for cnttzw " & to_hstring(rs)));
report "bad cnttzw " & to_hstring(rs) & " -> " & to_hstring(result);
end if; end if;
r := r(62 downto 0) & '0'; r := r(62 downto 0) & '0';
end loop; end loop;

76
divider_tb.vhdl
View File

@ -67,7 +67,7 @@ begin
d1.divisor <= x"0000000000001111"; d1.divisor <= x"0000000000001111";
wait for clk_period; wait for clk_period;
assert d2.valid = '0'; check_false(?? d2.valid, result("for valid"));
d1.valid <= '0'; d1.valid <= '0';
@ -78,16 +78,16 @@ begin
end if; end if;
end loop; end loop;
assert d2.valid = '1'; check_true(?? d2.valid, result("for valid"));
assert d2.write_reg_data = x"000000000000f001" report "result " & to_hstring(d2.write_reg_data); check_equal(d2.write_reg_data, 16#f001#);
wait for clk_period; wait for clk_period;
assert d2.valid = '0' report "valid"; check_false(?? d2.valid, result("for valid"));
d1.valid <= '1'; d1.valid <= '1';
wait for clk_period; wait for clk_period;
assert d2.valid = '0' report "valid"; check_false(?? d2.valid, result("for valid"));
d1.valid <= '0'; d1.valid <= '0';
@ -98,11 +98,11 @@ begin
end if; end if;
end loop; end loop;
assert d2.valid = '1'; check_true(?? d2.valid, result("for valid"));
assert d2.write_reg_data = x"000000000000f001" report "result " & to_hstring(d2.write_reg_data); check_equal(d2.write_reg_data, 16#f001#);
wait for clk_period; wait for clk_period;
assert d2.valid = '0'; check_false(?? d2.valid, result("for valid"));
elsif run("Test divd") then elsif run("Test divd") then
divd_loop : for dlength in 1 to 8 loop divd_loop : for dlength in 1 to 8 loop
@ -126,14 +126,13 @@ begin
exit; exit;
end if; end if;
end loop; end loop;
assert d2.valid = '1'; check_true(?? d2.valid, result("for valid"));
behave_rt := (others => '0'); behave_rt := (others => '0');
if rb /= x"0000000000000000" and (ra /= x"8000000000000000" or rb /= x"ffffffffffffffff") then if rb /= x"0000000000000000" and (ra /= x"8000000000000000" or rb /= x"ffffffffffffffff") then
behave_rt := ppc_divd(ra, rb); behave_rt := ppc_divd(ra, rb);
end if; end if;
assert to_hstring(behave_rt) = to_hstring(d2.write_reg_data) check_equal(d2.write_reg_data, behave_rt, result("for divd"));
report "bad divd expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
end loop; end loop;
end loop; end loop;
end loop; end loop;
@ -158,14 +157,13 @@ begin
exit; exit;
end if; end if;
end loop; end loop;
assert d2.valid = '1'; check_true(?? d2.valid, result("for valid"));
behave_rt := (others => '0'); behave_rt := (others => '0');
if rb /= x"0000000000000000" then if rb /= x"0000000000000000" then
behave_rt := ppc_divdu(ra, rb); behave_rt := ppc_divdu(ra, rb);
end if; end if;
assert to_hstring(behave_rt) = to_hstring(d2.write_reg_data) check_equal(d2.write_reg_data, behave_rt, result("for divdu"));
report "bad divdu expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
end loop; end loop;
end loop; end loop;
end loop; end loop;
@ -193,7 +191,7 @@ begin
exit; exit;
end if; end if;
end loop; end loop;
assert d2.valid = '1'; check_true(?? d2.valid, result("for valid"));
behave_rt := (others => '0'); behave_rt := (others => '0');
if rb /= x"0000000000000000" then if rb /= x"0000000000000000" then
@ -204,8 +202,7 @@ begin
behave_rt := q128(63 downto 0); behave_rt := q128(63 downto 0);
end if; end if;
end if; end if;
assert to_hstring(behave_rt) = to_hstring(d2.write_reg_data) check_equal(d2.write_reg_data, behave_rt, result("for divde"));
report "bad divde expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data) & " for ra = " & to_hstring(ra) & " rb = " & to_hstring(rb);
end loop; end loop;
end loop; end loop;
end loop; end loop;
@ -231,7 +228,7 @@ begin
exit; exit;
end if; end if;
end loop; end loop;
assert d2.valid = '1'; check_true(?? d2.valid, result("for valid"));
behave_rt := (others => '0'); behave_rt := (others => '0');
if unsigned(rb) > unsigned(ra) then if unsigned(rb) > unsigned(ra) then
@ -239,8 +236,7 @@ begin
q128 := std_ulogic_vector(unsigned(d128) / unsigned(rb)); q128 := std_ulogic_vector(unsigned(d128) / unsigned(rb));
behave_rt := q128(63 downto 0); behave_rt := q128(63 downto 0);
end if; end if;
assert to_hstring(behave_rt) = to_hstring(d2.write_reg_data) check_equal(d2.write_reg_data, behave_rt, result("for divdeu"));
report "bad divdeu expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data) & " for ra = " & to_hstring(ra) & " rb = " & to_hstring(rb);
end loop; end loop;
end loop; end loop;
end loop; end loop;
@ -268,14 +264,13 @@ begin
exit; exit;
end if; end if;
end loop; end loop;
assert d2.valid = '1'; check_true(?? d2.valid, result("for valid"));
behave_rt := (others => '0'); behave_rt := (others => '0');
if rb /= x"0000000000000000" and (ra /= x"ffffffff80000000" or rb /= x"ffffffffffffffff") then if rb /= x"0000000000000000" and (ra /= x"ffffffff80000000" or rb /= x"ffffffffffffffff") then
behave_rt := ppc_divw(ra, rb); behave_rt := ppc_divw(ra, rb);
end if; end if;
assert behave_rt = d2.write_reg_data check_equal(d2.write_reg_data, behave_rt, result("for divw"));
report "bad divw expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
end loop; end loop;
end loop; end loop;
end loop; end loop;
@ -301,14 +296,13 @@ begin
exit; exit;
end if; end if;
end loop; end loop;
assert d2.valid = '1'; check_true(?? d2.valid, result("for valid"));
behave_rt := (others => '0'); behave_rt := (others => '0');
if rb /= x"0000000000000000" then if rb /= x"0000000000000000" then
behave_rt := ppc_divwu(ra, rb); behave_rt := ppc_divwu(ra, rb);
end if; end if;
assert behave_rt = d2.write_reg_data check_equal(d2.write_reg_data, behave_rt, result("for divwu"));
report "bad divwu expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
end loop; end loop;
end loop; end loop;
end loop; end loop;
@ -336,7 +330,7 @@ begin
exit; exit;
end if; end if;
end loop; end loop;
assert d2.valid = '1'; check_true(?? d2.valid, result("for valid"));
behave_rt := (others => '0'); behave_rt := (others => '0');
if rb /= x"0000000000000000" then if rb /= x"0000000000000000" then
@ -345,8 +339,7 @@ begin
q64(63 downto 31) = x"ffffffff" & '1' then q64(63 downto 31) = x"ffffffff" & '1' then
behave_rt := x"00000000" & q64(31 downto 0); behave_rt := x"00000000" & q64(31 downto 0);
end if; end if;
assert behave_rt = d2.write_reg_data check_equal(d2.write_reg_data, behave_rt, result("for divwe"));
report "bad divwe expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data) & " for ra = " & to_hstring(ra) & " rb = " & to_hstring(rb);
end if; end if;
end loop; end loop;
end loop; end loop;
@ -373,14 +366,13 @@ begin
exit; exit;
end if; end if;
end loop; end loop;
assert d2.valid = '1'; check_true(?? d2.valid, result("for valid"));
behave_rt := (others => '0'); behave_rt := (others => '0');
if unsigned(rb(31 downto 0)) > unsigned(ra(63 downto 32)) then if unsigned(rb(31 downto 0)) > unsigned(ra(63 downto 32)) then
behave_rt := std_ulogic_vector(unsigned(ra) / unsigned(rb)); behave_rt := std_ulogic_vector(unsigned(ra) / unsigned(rb));
end if; end if;
assert behave_rt = d2.write_reg_data check_equal(d2.write_reg_data, behave_rt, result("for divweu"));
report "bad divweu expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data) & " for ra = " & to_hstring(ra) & " rb = " & to_hstring(rb);
end loop; end loop;
end loop; end loop;
end loop; end loop;
@ -408,14 +400,13 @@ begin
exit; exit;
end if; end if;
end loop; end loop;
assert d2.valid = '1'; check_true(?? d2.valid, result("for valid"));
behave_rt := (others => '0'); behave_rt := (others => '0');
if rb /= x"0000000000000000" then if rb /= x"0000000000000000" then
behave_rt := std_ulogic_vector(signed(ra) rem signed(rb)); behave_rt := std_ulogic_vector(signed(ra) rem signed(rb));
end if; end if;
assert behave_rt = d2.write_reg_data check_equal(d2.write_reg_data, behave_rt, result("for modsd"));
report "bad modsd expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
end loop; end loop;
end loop; end loop;
end loop; end loop;
@ -441,14 +432,13 @@ begin
exit; exit;
end if; end if;
end loop; end loop;
assert d2.valid = '1'; check_true(?? d2.valid, result("for valid"));
behave_rt := (others => '0'); behave_rt := (others => '0');
if rb /= x"0000000000000000" then if rb /= x"0000000000000000" then
behave_rt := std_ulogic_vector(unsigned(ra) rem unsigned(rb)); behave_rt := std_ulogic_vector(unsigned(ra) rem unsigned(rb));
end if; end if;
assert behave_rt = d2.write_reg_data check_equal(d2.write_reg_data, behave_rt, result("for modud"));
report "bad modud expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
end loop; end loop;
end loop; end loop;
end loop; end loop;
@ -477,7 +467,7 @@ begin
exit; exit;
end if; end if;
end loop; end loop;
assert d2.valid = '1'; check_true(?? d2.valid, result("for valid"));
behave_rt := (others => '0'); behave_rt := (others => '0');
if rb /= x"0000000000000000" then if rb /= x"0000000000000000" then
@ -488,8 +478,7 @@ begin
behave_rt := x"ffffffff" & rem32; behave_rt := x"ffffffff" & rem32;
end if; end if;
end if; end if;
assert behave_rt = d2.write_reg_data check_equal(d2.write_reg_data, behave_rt, result("for modsw"));
report "bad modsw expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
end loop; end loop;
end loop; end loop;
end loop; end loop;
@ -516,14 +505,13 @@ begin
exit; exit;
end if; end if;
end loop; end loop;
assert d2.valid = '1'; check_true(?? d2.valid, result("for valid"));
behave_rt := (others => '0'); behave_rt := (others => '0');
if rb /= x"0000000000000000" then if rb /= x"0000000000000000" then
behave_rt := x"00000000" & std_ulogic_vector(unsigned(ra(31 downto 0)) rem unsigned(rb(31 downto 0))); behave_rt := x"00000000" & std_ulogic_vector(unsigned(ra(31 downto 0)) rem unsigned(rb(31 downto 0)));
end if; end if;
assert behave_rt(31 downto 0) = d2.write_reg_data(31 downto 0) check_equal(d2.write_reg_data(31 downto 0), behave_rt(31 downto 0), result("for moduw"));
report "bad moduw expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
end loop; end loop;
end loop; end loop;
end loop; end loop;

62
multiply_tb.vhdl
View File

@ -67,33 +67,33 @@ begin
m1.data2 <= x"0000000000001111"; m1.data2 <= x"0000000000001111";
wait for clk_period; wait for clk_period;
assert m2.valid = '0'; check_false(?? m2.valid, result("for valid"));
m1.valid <= '0'; m1.valid <= '0';
wait for clk_period; wait for clk_period;
assert m2.valid = '0'; check_false(?? m2.valid, result("for valid"));
wait for clk_period; wait for clk_period;
assert m2.valid = '0'; check_false(?? m2.valid, result("for valid"));
wait for clk_period; wait for clk_period;
assert m2.valid = '1'; check_true(?? m2.valid, result("for valid"));
assert m2.result = x"00000000000000000000000001111000"; check_equal(m2.result, 16#1111000#);
wait for clk_period; wait for clk_period;
assert m2.valid = '0'; check_false(?? m2.valid, result("for valid"));
m1.valid <= '1'; m1.valid <= '1';
wait for clk_period; wait for clk_period;
assert m2.valid = '0'; check_false(?? m2.valid, result("for valid"));
m1.valid <= '0'; m1.valid <= '0';
wait for clk_period * (pipeline_depth-1); wait for clk_period * (pipeline_depth-1);
assert m2.valid = '1'; check_true(?? m2.valid, result("for valid"));
assert m2.result = x"00000000000000000000000001111000"; check_equal(m2.result, 16#1111000#);
elsif run("Test mulld") then elsif run("Test mulld") then
mulld_loop : for i in 0 to 1000 loop mulld_loop : for i in 0 to 1000 loop
@ -115,10 +115,8 @@ begin
wait for clk_period * (pipeline_depth-1); wait for clk_period * (pipeline_depth-1);
assert m2.valid = '1'; check_true(?? m2.valid, result("for valid"));
check_equal(m2.result(63 downto 0), behave_rt, result("for mulld " & to_hstring(behave_rt)));
assert to_hstring(behave_rt) = to_hstring(m2.result(63 downto 0))
report "bad mulld expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.result(63 downto 0));
end loop; end loop;
elsif run("Test mulhdu") then elsif run("Test mulhdu") then
@ -140,10 +138,8 @@ begin
wait for clk_period * (pipeline_depth-1); wait for clk_period * (pipeline_depth-1);
assert m2.valid = '1'; check_true(?? m2.valid, result("for valid"));
check_equal(m2.result(127 downto 64), behave_rt, result("for mulhdu " & to_hstring(behave_rt)));
assert to_hstring(behave_rt) = to_hstring(m2.result(127 downto 64))
report "bad mulhdu expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.result(127 downto 64));
end loop; end loop;
elsif run("Test mulhd") then elsif run("Test mulhd") then
@ -166,10 +162,8 @@ begin
wait for clk_period * (pipeline_depth-1); wait for clk_period * (pipeline_depth-1);
assert m2.valid = '1'; check_true(?? m2.valid, result("for valid"));
check_equal(m2.result(127 downto 64), behave_rt, result("for mulhd " & to_hstring(behave_rt)));
assert to_hstring(behave_rt) = to_hstring(m2.result(127 downto 64))
report "bad mulhd expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.result(127 downto 64));
end loop; end loop;
elsif run("Test mullw") then elsif run("Test mullw") then
@ -194,10 +188,8 @@ begin
wait for clk_period * (pipeline_depth-1); wait for clk_period * (pipeline_depth-1);
assert m2.valid = '1'; check_true(?? m2.valid, result("for valid"));
check_equal(m2.result(63 downto 0), behave_rt, result("for mullw " & to_hstring(behave_rt)));
assert to_hstring(behave_rt) = to_hstring(m2.result(63 downto 0))
report "bad mullw expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.result(63 downto 0));
end loop; end loop;
elsif run("Test mulhw") then elsif run("Test mulhw") then
@ -222,11 +214,8 @@ begin
wait for clk_period * (pipeline_depth-1); wait for clk_period * (pipeline_depth-1);
assert m2.valid = '1'; check_true(?? m2.valid, result("for valid"));
check_equal(m2.result(63 downto 32) & m2.result(63 downto 32), behave_rt, result("for mulhw " & to_hstring(behave_rt)));
assert to_hstring(behave_rt) = to_hstring(m2.result(63 downto 32) & m2.result(63 downto 32))
report "bad mulhw expected " & to_hstring(behave_rt) & " got " &
to_hstring(m2.result(63 downto 32) & m2.result(63 downto 32));
end loop; end loop;
elsif run("Test mulhwu") then elsif run("Test mulhwu") then
@ -250,11 +239,8 @@ begin
wait for clk_period * (pipeline_depth-1); wait for clk_period * (pipeline_depth-1);
assert m2.valid = '1'; check_true(?? m2.valid, result("for valid"));
check_equal(m2.result(63 downto 32) & m2.result(63 downto 32), behave_rt, result("for mulhwu " & to_hstring(behave_rt)));
assert to_hstring(behave_rt) = to_hstring(m2.result(63 downto 32) & m2.result(63 downto 32))
report "bad mulhwu expected " & to_hstring(behave_rt) & " got " &
to_hstring(m2.result(63 downto 32) & m2.result(63 downto 32));
end loop; end loop;
elsif run("Test mulli") then elsif run("Test mulli") then
@ -278,10 +264,8 @@ begin
wait for clk_period * (pipeline_depth-1); wait for clk_period * (pipeline_depth-1);
assert m2.valid = '1'; check_true(?? m2.valid, result("for valid"));
check_equal(m2.result(63 downto 0), behave_rt, result("for mulli " & to_hstring(behave_rt)));
assert to_hstring(behave_rt) = to_hstring(m2.result(63 downto 0))
report "bad mulli expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.result(63 downto 0));
end loop; end loop;
end if; end if;
end loop; end loop;

40
plru_tb.vhdl
View File

@ -58,56 +58,56 @@ begin
wait for 4*clk_period; wait for 4*clk_period;
report "accessing 1:"; info("accessing 1:");
acc <= "001"; acc <= "001";
acc_en <= '1'; acc_en <= '1';
wait for clk_period; wait for clk_period;
report "lru:" & to_hstring(lru); info("lru:" & to_hstring(lru));
report "accessing 2:"; info("accessing 2:");
acc <= "010"; acc <= "010";
wait for clk_period; wait for clk_period;
report "lru:" & to_hstring(lru); info("lru:" & to_hstring(lru));
report "accessing 7:"; info("accessing 7:");
acc <= "111"; acc <= "111";
wait for clk_period; wait for clk_period;
report "lru:" & to_hstring(lru); info("lru:" & to_hstring(lru));
report "accessing 4:"; info("accessing 4:");
acc <= "100"; acc <= "100";
wait for clk_period; wait for clk_period;
report "lru:" & to_hstring(lru); info("lru:" & to_hstring(lru));
report "accessing 3:"; info("accessing 3:");
acc <= "011"; acc <= "011";
wait for clk_period; wait for clk_period;
report "lru:" & to_hstring(lru); info("lru:" & to_hstring(lru));
report "accessing 5:"; info("accessing 5:");
acc <= "101"; acc <= "101";
wait for clk_period; wait for clk_period;
report "lru:" & to_hstring(lru); info("lru:" & to_hstring(lru));
report "accessing 3:"; info("accessing 3:");
acc <= "011"; acc <= "011";
wait for clk_period; wait for clk_period;
report "lru:" & to_hstring(lru); info("lru:" & to_hstring(lru));
report "accessing 5:"; info("accessing 5:");
acc <= "101"; acc <= "101";
wait for clk_period; wait for clk_period;
report "lru:" & to_hstring(lru); info("lru:" & to_hstring(lru));
report "accessing 6:"; info("accessing 6:");
acc <= "110"; acc <= "110";
wait for clk_period; wait for clk_period;
report "lru:" & to_hstring(lru); info("lru:" & to_hstring(lru));
report "accessing 0:"; info("accessing 0:");
acc <= "000"; acc <= "000";
wait for clk_period; wait for clk_period;
report "lru:" & to_hstring(lru); info("lru:" & to_hstring(lru));
test_runner_cleanup(runner); test_runner_cleanup(runner);
end process; end process;

83
rotator_tb.vhdl
View File

@ -23,7 +23,7 @@ architecture behave of rotator_tb is
signal shift: std_ulogic_vector(6 downto 0) := (others => '0'); signal shift: std_ulogic_vector(6 downto 0) := (others => '0');
signal insn: std_ulogic_vector(31 downto 0) := (others => '0'); signal insn: std_ulogic_vector(31 downto 0) := (others => '0');
signal is_32bit, right_shift, arith, clear_left, clear_right: std_ulogic := '0'; signal is_32bit, right_shift, arith, clear_left, clear_right: std_ulogic := '0';
signal result: std_ulogic_vector(63 downto 0); signal res: std_ulogic_vector(63 downto 0);
signal carry_out: std_ulogic; signal carry_out: std_ulogic;
signal extsw: std_ulogic; signal extsw: std_ulogic;
@ -40,7 +40,7 @@ begin
clear_left => clear_left, clear_left => clear_left,
clear_right => clear_right, clear_right => clear_right,
sign_ext_rs => extsw, sign_ext_rs => extsw,
result => result, result => res,
carry_out => carry_out carry_out => carry_out
); );
@ -51,6 +51,10 @@ begin
begin begin
rnd.InitSeed(stim_process'path_name); rnd.InitSeed(stim_process'path_name);
-- TODO: Consider making debug messages visible with a command line option
-- rather than uncommenting this line:
-- show(display_handler, debug);
test_runner_setup(runner, runner_cfg); test_runner_setup(runner, runner_cfg);
while test_suite loop while test_suite loop
@ -68,8 +72,7 @@ begin
insn <= x"00000" & '0' & rnd.RandSlv(10) & '0'; insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
wait for clk_period; wait for clk_period;
behave_ra := ppc_rlwinm(rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn)); behave_ra := ppc_rlwinm(rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn));
assert behave_ra = result check_equal(res, behave_ra, result("for rlwnm"));
report "bad rlwnm expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;
elsif run("Test rlwimi") then elsif run("Test rlwimi") then
@ -85,8 +88,7 @@ begin
insn <= x"00000" & '0' & rnd.RandSlv(10) & '0'; insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
wait for clk_period; wait for clk_period;
behave_ra := ppc_rlwimi(ra, rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn)); behave_ra := ppc_rlwimi(ra, rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn));
assert behave_ra = result check_equal(res, behave_ra, result("for rlwnimi"));
report "bad rlwimi expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;
elsif run("Test rld[i]cl") then elsif run("Test rld[i]cl") then
@ -102,8 +104,7 @@ begin
insn <= x"00000" & '0' & rnd.RandSlv(10) & '0'; insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
wait for clk_period; wait for clk_period;
behave_ra := ppc_rldicl(rs, shift(5 downto 0), insn_mb(insn)); behave_ra := ppc_rldicl(rs, shift(5 downto 0), insn_mb(insn));
assert behave_ra = result check_equal(res, behave_ra, result("for rldicl"));
report "bad rldicl expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;
elsif run("Test rld[i]cr") then elsif run("Test rld[i]cr") then
@ -119,13 +120,12 @@ begin
insn <= x"00000" & '0' & rnd.RandSlv(10) & '0'; insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
wait for clk_period; wait for clk_period;
behave_ra := ppc_rldicr(rs, shift(5 downto 0), insn_me(insn)); behave_ra := ppc_rldicr(rs, shift(5 downto 0), insn_me(insn));
--report "rs = " & to_hstring(rs); debug("rs = " & to_hstring(rs));
--report "ra = " & to_hstring(ra); debug("ra = " & to_hstring(ra));
--report "shift = " & to_hstring(shift); debug("shift = " & to_hstring(shift));
--report "insn me = " & to_hstring(insn_me(insn)); debug("insn me = " & to_hstring(insn_me(insn)));
--report "result = " & to_hstring(result); debug("result = " & to_hstring(res));
assert behave_ra = result check_equal(res, behave_ra, result("for rldicr"));
report "bad rldicr expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;
elsif run("Test rldic") then elsif run("Test rldic") then
@ -141,8 +141,7 @@ begin
insn <= x"00000" & '0' & rnd.RandSlv(10) & '0'; insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
wait for clk_period; wait for clk_period;
behave_ra := ppc_rldic(rs, shift(5 downto 0), insn_mb(insn)); behave_ra := ppc_rldic(rs, shift(5 downto 0), insn_mb(insn));
assert behave_ra = result check_equal(res, behave_ra, result("for rldic"));
report "bad rldic expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;
elsif run("Test rldimi") then elsif run("Test rldimi") then
@ -158,8 +157,7 @@ begin
insn <= x"00000" & '0' & rnd.RandSlv(10) & '0'; insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
wait for clk_period; wait for clk_period;
behave_ra := ppc_rldimi(ra, rs, shift(5 downto 0), insn_mb(insn)); behave_ra := ppc_rldimi(ra, rs, shift(5 downto 0), insn_mb(insn));
assert behave_ra = result check_equal(res, behave_ra, result("for rldimi"));
report "bad rldimi expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;
elsif run("Test slw") then elsif run("Test slw") then
@ -174,8 +172,7 @@ begin
shift <= rnd.RandSlv(7); shift <= rnd.RandSlv(7);
wait for clk_period; wait for clk_period;
behave_ra := ppc_slw(rs, std_ulogic_vector(resize(unsigned(shift), 64))); behave_ra := ppc_slw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
assert behave_ra = result check_equal(res, behave_ra, result("for slv"));
report "bad slw expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;
elsif run("Test sld") then elsif run("Test sld") then
@ -190,8 +187,7 @@ begin
shift <= rnd.RandSlv(7); shift <= rnd.RandSlv(7);
wait for clk_period; wait for clk_period;
behave_ra := ppc_sld(rs, std_ulogic_vector(resize(unsigned(shift), 64))); behave_ra := ppc_sld(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
assert behave_ra = result check_equal(res, behave_ra, result("for sld"));
report "bad sld expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;
elsif run("Test srw") then elsif run("Test srw") then
@ -206,8 +202,7 @@ begin
shift <= rnd.RandSlv(7); shift <= rnd.RandSlv(7);
wait for clk_period; wait for clk_period;
behave_ra := ppc_srw(rs, std_ulogic_vector(resize(unsigned(shift), 64))); behave_ra := ppc_srw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
assert behave_ra = result check_equal(res, behave_ra, result("for srw"));
report "bad srw expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;
elsif run("Test srd") then elsif run("Test srd") then
@ -222,8 +217,7 @@ begin
shift <= rnd.RandSlv(7); shift <= rnd.RandSlv(7);
wait for clk_period; wait for clk_period;
behave_ra := ppc_srd(rs, std_ulogic_vector(resize(unsigned(shift), 64))); behave_ra := ppc_srd(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
assert behave_ra = result check_equal(res, behave_ra, result("for srd"));
report "bad srd expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;
elsif run("Test sraw[i]") then elsif run("Test sraw[i]") then
@ -238,12 +232,12 @@ begin
shift <= '0' & rnd.RandSlv(6); shift <= '0' & rnd.RandSlv(6);
wait for clk_period; wait for clk_period;
behave_ca_ra := ppc_sraw(rs, std_ulogic_vector(resize(unsigned(shift), 64))); behave_ca_ra := ppc_sraw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
--report "rs = " & to_hstring(rs); debug("rs = " & to_hstring(rs));
--report "ra = " & to_hstring(ra); debug("ra = " & to_hstring(ra));
--report "shift = " & to_hstring(shift); debug("shift = " & to_hstring(shift));
--report "result = " & to_hstring(carry_out & result); debug("result = " & to_hstring(carry_out & res));
assert behave_ca_ra(63 downto 0) = result and behave_ca_ra(64) = carry_out check_equal(res, behave_ca_ra(63 downto 0), result("for sraw"));
report "bad sraw expected " & to_hstring(behave_ca_ra) & " got " & to_hstring(carry_out & result); check_equal(carry_out, behave_ca_ra(64), result("for sraw carry_out"));
end loop; end loop;
elsif run("Test srad[i]") then elsif run("Test srad[i]") then
@ -258,12 +252,12 @@ begin
shift <= rnd.RandSlv(7); shift <= rnd.RandSlv(7);
wait for clk_period; wait for clk_period;
behave_ca_ra := ppc_srad(rs, std_ulogic_vector(resize(unsigned(shift), 64))); behave_ca_ra := ppc_srad(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
--report "rs = " & to_hstring(rs); debug("rs = " & to_hstring(rs));
--report "ra = " & to_hstring(ra); debug("ra = " & to_hstring(ra));
--report "shift = " & to_hstring(shift); debug("shift = " & to_hstring(shift));
--report "result = " & to_hstring(carry_out & result); debug("result = " & to_hstring(carry_out & res));
assert behave_ca_ra(63 downto 0) = result and behave_ca_ra(64) = carry_out check_equal(res, behave_ca_ra(63 downto 0), result("for srad"));
report "bad srad expected " & to_hstring(behave_ca_ra) & " got " & to_hstring(carry_out & result); check_equal(carry_out, behave_ca_ra(64), result("for srad carry_out"));
end loop; end loop;
elsif run("Test extswsli") then elsif run("Test extswsli") then
@ -282,12 +276,11 @@ begin
behave_ra(63 downto 32) := (others => rs(31)); behave_ra(63 downto 32) := (others => rs(31));
behave_ra := std_ulogic_vector(shift_left(unsigned(behave_ra), behave_ra := std_ulogic_vector(shift_left(unsigned(behave_ra),
to_integer(unsigned(shift)))); to_integer(unsigned(shift))));
--report "rs = " & to_hstring(rs); debug("rs = " & to_hstring(rs));
--report "ra = " & to_hstring(ra); debug("ra = " & to_hstring(ra));
--report "shift = " & to_hstring(shift); debug("shift = " & to_hstring(shift));
--report "result = " & to_hstring(carry_out & result); debug("result = " & to_hstring(carry_out & res));
assert behave_ra = result check_equal(res, behave_ra, result("for extswsli"));
report "bad extswsli expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;
end if; end if;
end loop; end loop;

8
run.py
View File

@ -7,8 +7,8 @@ prj.add_osvvm()
root = Path(__file__).parent root = Path(__file__).parent
lib = prj.add_library("lib") lib = prj.add_library("lib")
lib.add_source_files(root / "litedram/extras/*.vhdl") lib.add_source_files(root / "litedram" / "extras" / "*.vhdl")
lib.add_source_files(root / "litedram/generated/sim/*.vhdl") lib.add_source_files(root / "litedram" / "generated" / "sim" / "*.vhdl")
# Use multiply.vhd and not xilinx-mult.vhd. Use VHDL-based random. # Use multiply.vhd and not xilinx-mult.vhd. Use VHDL-based random.
vhdl_files = glob(str(root / "*.vhdl")) vhdl_files = glob(str(root / "*.vhdl"))
@ -22,6 +22,8 @@ vhdl_files = [
lib.add_source_files(vhdl_files) lib.add_source_files(vhdl_files)
unisim = prj.add_library("unisim") unisim = prj.add_library("unisim")
unisim.add_source_files(root / "sim-unisim/*.vhdl") unisim.add_source_files(root / "sim-unisim" / "*.vhdl")
prj.set_sim_option("disable_ieee_warnings", True)
prj.main() prj.main()