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uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl

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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Benjamin Herrenschmidt
2020-06-18 11:18:30 +10:00
parent e3941109af
commit 4eae29801b
3 changed files with 2 additions and 2 deletions
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2
scripts/dependencies.py
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@@ -39,7 +39,7 @@ sim_provides = {
"dmi_dtm" : "dmi_dtm_xilinx.vhdl",
"clock_generator" : "fpga/clk_gen_bypass.vhd",
"main_bram" : "sim_bram.vhdl",
"pp_soc_uart" : "sim_uart.vhdl"
"pp_soc_uart" : "sim_pp_uart.vhdl"
}
if synth: