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uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl

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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt 2020-06-18 11:18:30 +10:00
parent e3941109af
commit 4eae29801b
3 changed files with 2 additions and 2 deletions
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2
Makefile
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@ -55,7 +55,7 @@ soc_files = $(core_files) wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_
spi_rxtx.vhdl spi_flash_ctrl.vhdl spi_rxtx.vhdl spi_flash_ctrl.vhdl
soc_sim_files = $(soc_files) sim_console.vhdl sim_uart.vhdl sim_bram_helpers.vhdl \ soc_sim_files = $(soc_files) sim_console.vhdl sim_pp_uart.vhdl sim_bram_helpers.vhdl \
sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl dmi_dtm_xilinx.vhdl sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl dmi_dtm_xilinx.vhdl
soc_sim_c_files = sim_vhpi_c.c sim_bram_helpers_c.c sim_console_c.c \ soc_sim_c_files = sim_vhpi_c.c sim_bram_helpers_c.c sim_console_c.c \

2
scripts/dependencies.py
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@ -39,7 +39,7 @@ sim_provides = {
"dmi_dtm" : "dmi_dtm_xilinx.vhdl", "dmi_dtm" : "dmi_dtm_xilinx.vhdl",
"clock_generator" : "fpga/clk_gen_bypass.vhd", "clock_generator" : "fpga/clk_gen_bypass.vhd",
"main_bram" : "sim_bram.vhdl", "main_bram" : "sim_bram.vhdl",
"pp_soc_uart" : "sim_uart.vhdl" "pp_soc_uart" : "sim_pp_uart.vhdl"
} }
if synth: if synth:

0
sim_uart.vhdl → sim_pp_uart.vhdl
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