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execute1: Improve timing for execute bypass tag

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The tags for the bypass data paths back to decode2 don't really need
to depend on the stall/busy inputs or on whether an exception might be
generated, since the bypass values won't be used until the instruction
gets executed.  Therefore, this simplifies the expressions for
bypass_data.tag.valid and bypass_cr_data.tag.valid.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This commit is contained in:
Paul Mackerras 2025-01-04 16:27:10 +11:00
parent 80bc9d5098
commit 52d8f28d03
1 changed files with 8 additions and 9 deletions
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17
execute1.vhdl
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@ -1147,7 +1147,7 @@ begin
-- side-effect flags or write enables when generating a trap). -- side-effect flags or write enables when generating a trap).
-- With v.trap = 1 we will assert both ex1.e.valid and ex1.e.interrupt -- With v.trap = 1 we will assert both ex1.e.valid and ex1.e.interrupt
-- to writeback, and it will complete the instruction and take -- to writeback, and it will complete the instruction and take
-- and interrupt. It is OK for v.trap to depend on operand data. -- an interrupt. It is OK for v.trap to depend on operand data.
illegal := '0'; illegal := '0';
privileged := '0'; privileged := '0';
@ -1585,7 +1585,7 @@ begin
if e_in.unit = ALU then if e_in.unit = ALU then
v.complete := e_in.valid and not v.exception and not owait; v.complete := e_in.valid and not v.exception and not owait;
v.bypass_valid := e_in.valid and not v.exception and not slow_op; v.bypass_valid := e_in.valid and not slow_op;
end if; end if;
actions <= v; actions <= v;
@ -1631,7 +1631,7 @@ begin
v.taken_branch_event := '0'; v.taken_branch_event := '0';
v.br_mispredict := '0'; v.br_mispredict := '0';
v.busy := '0'; v.busy := '0';
bypass_valid := '0'; bypass_valid := actions.bypass_valid;
irq_valid := ex1.msr(MSR_EE) and (pmu_to_x.intr or ctrl.dec(63) or ext_irq_in); irq_valid := ex1.msr(MSR_EE) and (pmu_to_x.intr or ctrl.dec(63) or ext_irq_in);
@ -1706,7 +1706,6 @@ begin
if go = '1' then if go = '1' then
v.se := actions.se; v.se := actions.se;
v.e.valid := actions.complete; v.e.valid := actions.complete;
bypass_valid := actions.bypass_valid;
v.taken_branch_event := actions.take_branch; v.taken_branch_event := actions.take_branch;
v.trace_next := actions.do_trace or actions.ciabr_trace; v.trace_next := actions.do_trace or actions.ciabr_trace;
v.trace_ciabr := actions.ciabr_trace; v.trace_ciabr := actions.ciabr_trace;
@ -1814,13 +1813,13 @@ begin
v.fp_exception_next := '0'; v.fp_exception_next := '0';
end if; end if;
bypass_data.tag.valid <= v.e.write_enable and bypass_valid; bypass_data.tag.valid <= e_in.write_reg_enable and bypass_valid;
bypass_data.tag.tag <= v.e.instr_tag.tag; bypass_data.tag.tag <= e_in.instr_tag.tag;
bypass_data.data <= alu_result; bypass_data.data <= alu_result;
bypass_cr_data.tag.valid <= v.e.write_cr_enable and bypass_valid; bypass_cr_data.tag.valid <= e_in.output_cr and bypass_valid;
bypass_cr_data.tag.tag <= v.e.instr_tag.tag; bypass_cr_data.tag.tag <= e_in.instr_tag.tag;
bypass_cr_data.data <= v.e.write_cr_data; bypass_cr_data.data <= write_cr_data;
-- Outputs to loadstore1 (async) -- Outputs to loadstore1 (async)
lv.op := e_in.insn_type; lv.op := e_in.insn_type;