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litedram: Remove old "VexRiscV" based initializations
Support for this has bitrotted and would require refactoring of L2 to be brought back. It's also not really needed anymore now that we ship pre-generated litedram and that LiteX supports what we do. So take it out, which simplifies some of the scripts as well. This also fixes up CSR alignment the sim model. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt
@@ -1 +0,0 @@
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@@ -519,11 +519,11 @@ f8c101a838800140
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38c101987c651b78
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7fe3fb78f8e101b0
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f92101c0f90101b8
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48000d1df94101c8
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48000cfdf94101c8
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7c7e1b7860000000
|
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480008357fe3fb78
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480008157fe3fb78
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3821017060000000
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480012dc7fc3f378
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480012bc7fc3f378
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0100000000000000
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4e80002000000280
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0000000000000000
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@@ -534,256 +534,252 @@ f92101c0f90101b8
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7c0802a63842955c
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7d800026fbe1fff8
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91810008f8010010
|
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48000729f821ff91
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48000709f821ff91
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3c62ffff60000000
|
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4bffff3538637d60
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4bffff3538637d40
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548400023880ffff
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7c8026ea7c0004ac
|
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3fe0c0003c62ffff
|
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63ff000838637d80
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63ff000838637d60
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3c62ffff4bffff11
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38637da07bff0020
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38637d807bff0020
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7c0004ac4bffff01
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73e900017fe0feea
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3c62ffff41820010
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4bfffee538637db8
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4bfffee538637d98
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4d80000073e90002
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3c62ffff41820010
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4bfffecd38637dc0
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4bfffecd38637da0
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4e00000073e90004
|
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3c62ffff41820010
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4bfffeb538637dc8
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3bff7fc03fe2ffff
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4bfffeb538637da8
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3bff7fa03fe2ffff
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4bfffea57fe3fb78
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3c80c00041920028
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7884002060840010
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7c8026ea7c0004ac
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7884b2823c62ffff
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4bfffe7d38637dd0
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4bfffe7d38637db0
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3c80c000418e004c
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7884002060840018
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7c8026ea7c0004ac
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788465023c62ffff
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4bfffe5538637df0
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4bfffe5538637dd0
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608400303c80c000
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7c0004ac78840020
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3c62ffff7c8026ea
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38637e107884b282
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38637df07884b282
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3d20c0004bfffe31
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7929002061290020
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7d204eea7c0004ac
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3c62ffff3c80000f
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38637e3060844240
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38637e1060844240
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4bfffe057c892392
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4bfffdfd7fe3fb78
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3ca2ffff418e0028
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3c62ffff3c82ffff
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38847e6038a57e50
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4bfffddd38637e68
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6000000048000455
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38847e4038a57e30
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4bfffddd38637e48
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6000000048000419
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3c62ffff41920020
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4bfffdc538637e98
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4bfffdc538637e78
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8181000838210070
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||||
480010f87d818120
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38637eb03c62ffff
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480010d87d818120
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38637e903c62ffff
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3c80f0004bfffda9
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6084400038a0ffff
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7884002054a50422
|
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480007cd3c604000
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480007ad3c604000
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||||
3c62ffff60000000
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4bfffd7d38637ed0
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4bfffd7d38637eb0
|
||||
e801001038210070
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ebe1fff881810008
|
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7d8181207c0803a6
|
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000000004bfffde4
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||||
0000018003000000
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7869c0223d40c010
|
||||
794a0020614a080c
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7d20572a7c0004ac
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612908103d20c010
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612908043d20c010
|
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7c0004ac79290020
|
||||
4e8000207c604f2a
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||||
3d40c0107c604f2a
|
||||
614a080839200001
|
||||
7c0004ac794a0020
|
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4e8000207d20572a
|
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0000000000000000
|
||||
3d20c01000000000
|
||||
7929002061290804
|
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7c604f2a7c0004ac
|
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392000013d40c010
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||||
794a0020614a0808
|
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3c4c000100000000
|
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7c0802a63842930c
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614a08003d40c010
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794a002039200001
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||||
f821ffa1f8010010
|
||||
7d20572a7c0004ac
|
||||
000000004e800020
|
||||
0000000000000000
|
||||
384292d03c4c0001
|
||||
3d40c0107c0802a6
|
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39200001614a0800
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f8010010794a0020
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7c0004acf821ffa1
|
||||
3c62ffff7d20572a
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4bfffca538637fa0
|
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3821006060000000
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||||
7c0803a6e8010010
|
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000000004e800020
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0000008001000000
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384292783c4c0001
|
||||
390000807c0802a6
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3d40aaaa7d0903a6
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614aaaaa3d204000
|
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f821ff8148000f39
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3929000491490000
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4bfffcc14200fff8
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3940008060000000
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7d4903a63d00aaaa
|
||||
3be000003d204000
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814900006108aaaa
|
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419e000c7f8a4000
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7fff07b43bff0001
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4200ffe839290004
|
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3d40555539000080
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3d2040007d0903a6
|
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91490000614a5555
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38637f803c62ffff
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600000004bfffce1
|
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e801001038210060
|
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4e8000207c0803a6
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0100000000000000
|
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3c4c000100000080
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||||
7c0802a6384292b4
|
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7d0903a639000080
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3d2040003d40aaaa
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48000f55614aaaaa
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91490000f821ff81
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4200fff839290004
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600000004bfffc65
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3d00555539400080
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600000004bfffcfd
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3d00aaaa39400080
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||||
3d2040007d4903a6
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8149000061085555
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419e000c7f8a4000
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7fff07b43bff0001
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4200ffe839290004
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419e001c2fbf0000
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38a001003c62ffff
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38637ee87fe4fb78
|
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600000004bfffba1
|
||||
3ce0802039000100
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60e700037d0903a6
|
||||
392000013d404000
|
||||
7928f84278e70020
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||||
7d2900d0792907e0
|
||||
7d293838394a0004
|
||||
912afffc7d294278
|
||||
4bfffbd14200ffe4
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||||
6108aaaa3be00000
|
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7f8a400081490000
|
||||
3bff0001419e000c
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392900047fff07b4
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||||
390000804200ffe8
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||||
7d0903a63d405555
|
||||
614a55553d204000
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||||
3929000491490000
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4bfffca14200fff8
|
||||
3940008060000000
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7d4903a63d005555
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610855553d204000
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7f8a400081490000
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3bff0001419e000c
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392900047fff07b4
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2fbf00004200ffe8
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3c62ffff419e001c
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7fe4fb7838a00100
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4bfffbdd38637ec8
|
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3900010060000000
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7d0903a63ce08020
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3d40400060e70003
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392000013ba00000
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7928f84278e70020
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7d2900d0792907e0
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78e7002039200001
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||||
792907e07928f842
|
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394a00047d2900d0
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7d2942787d293838
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7f884840810a0000
|
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3bbd0001419e000c
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394a00047fbd07b4
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2fbd00004200ffd4
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3c62ffff419e001c
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7fa4eb7838a00100
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4bfffaed38637f10
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3920002060000000
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7d2903a639400000
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794800203d2a1000
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394a000139290002
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9109000079291764
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4bfffb314200ffe8
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3920002060000000
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7d2903a639400000
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||||
3d2a10003bc00000
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8129000879291764
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||||
7f8950005529043e
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3bde0001419e000c
|
||||
394a00017fde07b4
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||||
2fbe00004200ffdc
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||||
3c62ffff419e001c
|
||||
7fc4f37838a00020
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4bfffa6538637f38
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7fffea1460000000
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7ffff21438600000
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409e00ac2f9f0000
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38637f603c62ffff
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600000004bfffa41
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394000807c9602a6
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7d4903a678840020
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3d49080039200000
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||||
f92a0000794a1f24
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||||
4200fff039290001
|
||||
7c9f20507ff602a6
|
||||
63ff80003fe0000c
|
||||
4bfffa717fff2396
|
||||
7bff002060000000
|
||||
390000807d3602a6
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||||
7d0903a679290020
|
||||
e90a00003d404000
|
||||
4200fff8394a0008
|
||||
7d2548507cb602a6
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||||
60a580003ca0000c
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||||
7ca54b963c62ffff
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38637f707fe4fb78
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4bfff9ad78a50320
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3860000160000000
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48000cc438210080
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||||
0100000000000000
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||||
3c4c000100000380
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||||
7c0802a638428f84
|
||||
38637fc83c62ffff
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||||
f821ff7148000c49
|
||||
3bc000003f80c010
|
||||
7b9c0020639c1000
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||||
600000004bfff961
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||||
7fc0e72a7c0004ac
|
||||
637b10043f60c010
|
||||
7c0004ac7b7b0020
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||||
3fe0c0107fc0df2a
|
||||
63ff081438600000
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||||
7bff00204bfffbe1
|
||||
7fc0ff2a7c0004ac
|
||||
3920000c3fa0c010
|
||||
7bbd002063bd0800
|
||||
4200ffe4912afffc
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||||
600000004bfffc0d
|
||||
3ce0802039000100
|
||||
60e700037d0903a6
|
||||
3ba000003d404000
|
||||
78e7002039200001
|
||||
792907e07928f842
|
||||
7d2938387d2900d0
|
||||
810a00007d294278
|
||||
419e000c7f884840
|
||||
7fbd07b43bbd0001
|
||||
4200ffd4394a0004
|
||||
419e001c2fbd0000
|
||||
38a001003c62ffff
|
||||
38637ef07fa4eb78
|
||||
600000004bfffb29
|
||||
3940000039200020
|
||||
3d2a10007d2903a6
|
||||
3929000279480020
|
||||
79291764394a0001
|
||||
4200ffe891090000
|
||||
600000004bfffb6d
|
||||
3940000039200020
|
||||
3bc000007d2903a6
|
||||
792917643d2a1000
|
||||
5529043e81290008
|
||||
419e000c7f895000
|
||||
7fde07b43bde0001
|
||||
4200ffdc394a0001
|
||||
419e001c2fbe0000
|
||||
38a000203c62ffff
|
||||
38637f187fc4f378
|
||||
600000004bfffaa1
|
||||
386000007fffea14
|
||||
2f9f00007ffff214
|
||||
3c62ffff409e00ac
|
||||
4bfffa7d38637f40
|
||||
7c9602a660000000
|
||||
7884002039400080
|
||||
392000007d4903a6
|
||||
794a1f243d490800
|
||||
39290001f92a0000
|
||||
7ff602a64200fff0
|
||||
3fe0000c7c9f2050
|
||||
7fff239663ff8000
|
||||
600000004bfffaad
|
||||
7d3602a67bff0020
|
||||
7929002039000080
|
||||
3d4040007d0903a6
|
||||
394a0008e90a0000
|
||||
7cb602a64200fff8
|
||||
3ca0000c7d254850
|
||||
3c62ffff60a58000
|
||||
7fe4fb787ca54b96
|
||||
78a5032038637f50
|
||||
600000004bfff9e9
|
||||
3821008038600001
|
||||
0000000048000ce0
|
||||
0000038001000000
|
||||
38428fc03c4c0001
|
||||
3c62ffff7c0802a6
|
||||
48000c6138637fa8
|
||||
3f60c010f821ff71
|
||||
637b10003be00000
|
||||
4bfff99d7b7b0020
|
||||
7c0004ac60000000
|
||||
3f40c0107fe0df2a
|
||||
7b5a0020635a1004
|
||||
7fe0d72a7c0004ac
|
||||
63bd080c3fa0c010
|
||||
7c0004ac7bbd0020
|
||||
3fc0c0107fe0ef2a
|
||||
7bde002063de0810
|
||||
7fe0f72a7c0004ac
|
||||
3940000c3d20c010
|
||||
7929002061290800
|
||||
7d404f2a7c0004ac
|
||||
7fe0ef2a7c0004ac
|
||||
7fe0f72a7c0004ac
|
||||
7c0004ac3940000e
|
||||
392002007d404f2a
|
||||
7d20ef2a7c0004ac
|
||||
4bfffbb538600000
|
||||
7fc0ff2a7c0004ac
|
||||
7c0004ac3920000e
|
||||
386002007d20ef2a
|
||||
392000024bfffb99
|
||||
7d20ff2a7c0004ac
|
||||
4bfffbc13860000f
|
||||
4bfffb7d38600000
|
||||
7c0004ac39200003
|
||||
3860000f7d20ff2a
|
||||
4bfffba13ba00001
|
||||
4bfffb5d38600006
|
||||
7fa0ff2a7c0004ac
|
||||
4bfffb893860000f
|
||||
4bfffb4538600920
|
||||
7fc0ff2a7c0004ac
|
||||
4bfffb713860000f
|
||||
4bfffb2d38600400
|
||||
7fc0ff2a7c0004ac
|
||||
4bfffb5938600003
|
||||
4bfffbed4bfffb99
|
||||
7c0004ac39200002
|
||||
3860000f7d20f72a
|
||||
7c0004ac4bfffbb1
|
||||
392000037fe0ef2a
|
||||
7d20f72a7c0004ac
|
||||
4bfffb953860000f
|
||||
7c0004ac39200006
|
||||
3b8000017d20ef2a
|
||||
7f80f72a7c0004ac
|
||||
4bfffb753860000f
|
||||
7c0004ac39200920
|
||||
7c0004ac7d20ef2a
|
||||
3860000f7fe0f72a
|
||||
392004004bfffb59
|
||||
7d20ef2a7c0004ac
|
||||
7fe0f72a7c0004ac
|
||||
4bfffb3d38600003
|
||||
4bfffbd14bfffb7d
|
||||
4082001c2c230000
|
||||
7fa0e72a7c0004ac
|
||||
7fa0df2a7c0004ac
|
||||
48000b6438210090
|
||||
7fa0e72a7c0004ac
|
||||
7f80df2a7c0004ac
|
||||
7f80d72a7c0004ac
|
||||
48000b6038210090
|
||||
7f80df2a7c0004ac
|
||||
4bffffec38600001
|
||||
0100000000000000
|
||||
3c4c000100000580
|
||||
3d20c00038428e1c
|
||||
3c4c000100000680
|
||||
3d20c00038428e3c
|
||||
6129200060000000
|
||||
f922803079290020
|
||||
f922801079290020
|
||||
612900203d20c000
|
||||
7c0004ac79290020
|
||||
3d40001c7d204eea
|
||||
7d295392614a2000
|
||||
394a0018e9428030
|
||||
394a0018e9428010
|
||||
7c0004ac3929ffff
|
||||
4e8000207d2057ea
|
||||
0000000000000000
|
||||
3c4c000100000000
|
||||
6000000038428dbc
|
||||
39290010e9228030
|
||||
6000000038428ddc
|
||||
39290010e9228010
|
||||
7d204eea7c0004ac
|
||||
4082ffe871290008
|
||||
e94280305469063e
|
||||
e94280105469063e
|
||||
7d2057ea7c0004ac
|
||||
000000004e800020
|
||||
0000000000000000
|
||||
38428d783c4c0001
|
||||
38428d983c4c0001
|
||||
fbc1fff07c0802a6
|
||||
3bc3fffffbe1fff8
|
||||
f821ffd1f8010010
|
||||
@@ -857,7 +853,7 @@ f924000039290002
|
||||
7c6307b43863ffe0
|
||||
000000004e800020
|
||||
0000000000000000
|
||||
38428b283c4c0001
|
||||
38428b483c4c0001
|
||||
3d2037367c0802a6
|
||||
612935347d908026
|
||||
65293332792907c6
|
||||
@@ -891,7 +887,7 @@ fbfd00007fe9fa14
|
||||
4bfffff07d29f392
|
||||
0300000000000000
|
||||
3c4c000100000580
|
||||
7c0802a638428a1c
|
||||
7c0802a638428a3c
|
||||
f821ffb1480006e9
|
||||
7c7f1b78eb630000
|
||||
7cbd2b787c9c2378
|
||||
@@ -907,7 +903,7 @@ f821ffb1480006e9
|
||||
4bffffb8f93f0000
|
||||
0100000000000000
|
||||
3c4c000100000580
|
||||
7c0802a63842899c
|
||||
7c0802a6384289bc
|
||||
f821ffa148000661
|
||||
7c9b23787c7d1b78
|
||||
388000007ca32b78
|
||||
@@ -938,7 +934,7 @@ e95d00009b270000
|
||||
f95d0000394a0001
|
||||
000000004bffffa8
|
||||
0000078001000000
|
||||
384288a03c4c0001
|
||||
384288c03c4c0001
|
||||
480005397c0802a6
|
||||
7c741b79f821fed1
|
||||
38600000f8610060
|
||||
@@ -947,7 +943,7 @@ f95d0000394a0001
|
||||
3ac4ffff3e42ffff
|
||||
f92100703b410020
|
||||
3ae0000060000000
|
||||
3a527fe039228028
|
||||
3a527fc039228008
|
||||
f92100783ba10060
|
||||
ebc1006089250000
|
||||
419e00102fa90000
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
//--------------------------------------------------------------------------------
|
||||
// Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-02 11:27:39
|
||||
// Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-05 11:21:54
|
||||
//--------------------------------------------------------------------------------
|
||||
module litedram_core(
|
||||
input wire clk,
|
||||
@@ -33,8 +33,8 @@ module litedram_core(
|
||||
|
||||
reg [13:0] litedramcore_adr = 14'd0;
|
||||
reg litedramcore_we = 1'd0;
|
||||
wire [7:0] litedramcore_dat_w;
|
||||
wire [7:0] litedramcore_dat_r;
|
||||
wire [31:0] litedramcore_dat_w;
|
||||
wire [31:0] litedramcore_dat_r;
|
||||
wire [29:0] litedramcore_wishbone_adr;
|
||||
wire [31:0] litedramcore_wishbone_dat_w;
|
||||
wire [31:0] litedramcore_wishbone_dat_r;
|
||||
@@ -1638,8 +1638,8 @@ reg new_master_rdata_valid8 = 1'd0;
|
||||
reg new_master_rdata_valid9 = 1'd0;
|
||||
wire [13:0] interface0_bank_bus_adr;
|
||||
wire interface0_bank_bus_we;
|
||||
wire [7:0] interface0_bank_bus_dat_w;
|
||||
reg [7:0] interface0_bank_bus_dat_r = 8'd0;
|
||||
wire [31:0] interface0_bank_bus_dat_w;
|
||||
reg [31:0] interface0_bank_bus_dat_r = 32'd0;
|
||||
wire csrbank0_init_done0_re;
|
||||
wire csrbank0_init_done0_r;
|
||||
wire csrbank0_init_done0_we;
|
||||
@@ -1651,8 +1651,8 @@ wire csrbank0_init_error0_w;
|
||||
wire csrbank0_sel;
|
||||
wire [13:0] interface1_bank_bus_adr;
|
||||
wire interface1_bank_bus_we;
|
||||
wire [7:0] interface1_bank_bus_dat_w;
|
||||
reg [7:0] interface1_bank_bus_dat_r = 8'd0;
|
||||
wire [31:0] interface1_bank_bus_dat_w;
|
||||
reg [31:0] interface1_bank_bus_dat_r = 32'd0;
|
||||
wire csrbank1_dfii_control0_re;
|
||||
wire [3:0] csrbank1_dfii_control0_r;
|
||||
wire csrbank1_dfii_control0_we;
|
||||
@@ -1661,199 +1661,87 @@ wire csrbank1_dfii_pi0_command0_re;
|
||||
wire [5:0] csrbank1_dfii_pi0_command0_r;
|
||||
wire csrbank1_dfii_pi0_command0_we;
|
||||
wire [5:0] csrbank1_dfii_pi0_command0_w;
|
||||
wire csrbank1_dfii_pi0_address1_re;
|
||||
wire [5:0] csrbank1_dfii_pi0_address1_r;
|
||||
wire csrbank1_dfii_pi0_address1_we;
|
||||
wire [5:0] csrbank1_dfii_pi0_address1_w;
|
||||
wire csrbank1_dfii_pi0_address0_re;
|
||||
wire [7:0] csrbank1_dfii_pi0_address0_r;
|
||||
wire [13:0] csrbank1_dfii_pi0_address0_r;
|
||||
wire csrbank1_dfii_pi0_address0_we;
|
||||
wire [7:0] csrbank1_dfii_pi0_address0_w;
|
||||
wire [13:0] csrbank1_dfii_pi0_address0_w;
|
||||
wire csrbank1_dfii_pi0_baddress0_re;
|
||||
wire [2:0] csrbank1_dfii_pi0_baddress0_r;
|
||||
wire csrbank1_dfii_pi0_baddress0_we;
|
||||
wire [2:0] csrbank1_dfii_pi0_baddress0_w;
|
||||
wire csrbank1_dfii_pi0_wrdata3_re;
|
||||
wire [7:0] csrbank1_dfii_pi0_wrdata3_r;
|
||||
wire csrbank1_dfii_pi0_wrdata3_we;
|
||||
wire [7:0] csrbank1_dfii_pi0_wrdata3_w;
|
||||
wire csrbank1_dfii_pi0_wrdata2_re;
|
||||
wire [7:0] csrbank1_dfii_pi0_wrdata2_r;
|
||||
wire csrbank1_dfii_pi0_wrdata2_we;
|
||||
wire [7:0] csrbank1_dfii_pi0_wrdata2_w;
|
||||
wire csrbank1_dfii_pi0_wrdata1_re;
|
||||
wire [7:0] csrbank1_dfii_pi0_wrdata1_r;
|
||||
wire csrbank1_dfii_pi0_wrdata1_we;
|
||||
wire [7:0] csrbank1_dfii_pi0_wrdata1_w;
|
||||
wire csrbank1_dfii_pi0_wrdata0_re;
|
||||
wire [7:0] csrbank1_dfii_pi0_wrdata0_r;
|
||||
wire [31:0] csrbank1_dfii_pi0_wrdata0_r;
|
||||
wire csrbank1_dfii_pi0_wrdata0_we;
|
||||
wire [7:0] csrbank1_dfii_pi0_wrdata0_w;
|
||||
wire csrbank1_dfii_pi0_rddata3_re;
|
||||
wire [7:0] csrbank1_dfii_pi0_rddata3_r;
|
||||
wire csrbank1_dfii_pi0_rddata3_we;
|
||||
wire [7:0] csrbank1_dfii_pi0_rddata3_w;
|
||||
wire csrbank1_dfii_pi0_rddata2_re;
|
||||
wire [7:0] csrbank1_dfii_pi0_rddata2_r;
|
||||
wire csrbank1_dfii_pi0_rddata2_we;
|
||||
wire [7:0] csrbank1_dfii_pi0_rddata2_w;
|
||||
wire csrbank1_dfii_pi0_rddata1_re;
|
||||
wire [7:0] csrbank1_dfii_pi0_rddata1_r;
|
||||
wire csrbank1_dfii_pi0_rddata1_we;
|
||||
wire [7:0] csrbank1_dfii_pi0_rddata1_w;
|
||||
wire csrbank1_dfii_pi0_rddata0_re;
|
||||
wire [7:0] csrbank1_dfii_pi0_rddata0_r;
|
||||
wire csrbank1_dfii_pi0_rddata0_we;
|
||||
wire [7:0] csrbank1_dfii_pi0_rddata0_w;
|
||||
wire [31:0] csrbank1_dfii_pi0_wrdata0_w;
|
||||
wire csrbank1_dfii_pi0_rddata_re;
|
||||
wire [31:0] csrbank1_dfii_pi0_rddata_r;
|
||||
wire csrbank1_dfii_pi0_rddata_we;
|
||||
wire [31:0] csrbank1_dfii_pi0_rddata_w;
|
||||
wire csrbank1_dfii_pi1_command0_re;
|
||||
wire [5:0] csrbank1_dfii_pi1_command0_r;
|
||||
wire csrbank1_dfii_pi1_command0_we;
|
||||
wire [5:0] csrbank1_dfii_pi1_command0_w;
|
||||
wire csrbank1_dfii_pi1_address1_re;
|
||||
wire [5:0] csrbank1_dfii_pi1_address1_r;
|
||||
wire csrbank1_dfii_pi1_address1_we;
|
||||
wire [5:0] csrbank1_dfii_pi1_address1_w;
|
||||
wire csrbank1_dfii_pi1_address0_re;
|
||||
wire [7:0] csrbank1_dfii_pi1_address0_r;
|
||||
wire [13:0] csrbank1_dfii_pi1_address0_r;
|
||||
wire csrbank1_dfii_pi1_address0_we;
|
||||
wire [7:0] csrbank1_dfii_pi1_address0_w;
|
||||
wire [13:0] csrbank1_dfii_pi1_address0_w;
|
||||
wire csrbank1_dfii_pi1_baddress0_re;
|
||||
wire [2:0] csrbank1_dfii_pi1_baddress0_r;
|
||||
wire csrbank1_dfii_pi1_baddress0_we;
|
||||
wire [2:0] csrbank1_dfii_pi1_baddress0_w;
|
||||
wire csrbank1_dfii_pi1_wrdata3_re;
|
||||
wire [7:0] csrbank1_dfii_pi1_wrdata3_r;
|
||||
wire csrbank1_dfii_pi1_wrdata3_we;
|
||||
wire [7:0] csrbank1_dfii_pi1_wrdata3_w;
|
||||
wire csrbank1_dfii_pi1_wrdata2_re;
|
||||
wire [7:0] csrbank1_dfii_pi1_wrdata2_r;
|
||||
wire csrbank1_dfii_pi1_wrdata2_we;
|
||||
wire [7:0] csrbank1_dfii_pi1_wrdata2_w;
|
||||
wire csrbank1_dfii_pi1_wrdata1_re;
|
||||
wire [7:0] csrbank1_dfii_pi1_wrdata1_r;
|
||||
wire csrbank1_dfii_pi1_wrdata1_we;
|
||||
wire [7:0] csrbank1_dfii_pi1_wrdata1_w;
|
||||
wire csrbank1_dfii_pi1_wrdata0_re;
|
||||
wire [7:0] csrbank1_dfii_pi1_wrdata0_r;
|
||||
wire [31:0] csrbank1_dfii_pi1_wrdata0_r;
|
||||
wire csrbank1_dfii_pi1_wrdata0_we;
|
||||
wire [7:0] csrbank1_dfii_pi1_wrdata0_w;
|
||||
wire csrbank1_dfii_pi1_rddata3_re;
|
||||
wire [7:0] csrbank1_dfii_pi1_rddata3_r;
|
||||
wire csrbank1_dfii_pi1_rddata3_we;
|
||||
wire [7:0] csrbank1_dfii_pi1_rddata3_w;
|
||||
wire csrbank1_dfii_pi1_rddata2_re;
|
||||
wire [7:0] csrbank1_dfii_pi1_rddata2_r;
|
||||
wire csrbank1_dfii_pi1_rddata2_we;
|
||||
wire [7:0] csrbank1_dfii_pi1_rddata2_w;
|
||||
wire csrbank1_dfii_pi1_rddata1_re;
|
||||
wire [7:0] csrbank1_dfii_pi1_rddata1_r;
|
||||
wire csrbank1_dfii_pi1_rddata1_we;
|
||||
wire [7:0] csrbank1_dfii_pi1_rddata1_w;
|
||||
wire csrbank1_dfii_pi1_rddata0_re;
|
||||
wire [7:0] csrbank1_dfii_pi1_rddata0_r;
|
||||
wire csrbank1_dfii_pi1_rddata0_we;
|
||||
wire [7:0] csrbank1_dfii_pi1_rddata0_w;
|
||||
wire [31:0] csrbank1_dfii_pi1_wrdata0_w;
|
||||
wire csrbank1_dfii_pi1_rddata_re;
|
||||
wire [31:0] csrbank1_dfii_pi1_rddata_r;
|
||||
wire csrbank1_dfii_pi1_rddata_we;
|
||||
wire [31:0] csrbank1_dfii_pi1_rddata_w;
|
||||
wire csrbank1_dfii_pi2_command0_re;
|
||||
wire [5:0] csrbank1_dfii_pi2_command0_r;
|
||||
wire csrbank1_dfii_pi2_command0_we;
|
||||
wire [5:0] csrbank1_dfii_pi2_command0_w;
|
||||
wire csrbank1_dfii_pi2_address1_re;
|
||||
wire [5:0] csrbank1_dfii_pi2_address1_r;
|
||||
wire csrbank1_dfii_pi2_address1_we;
|
||||
wire [5:0] csrbank1_dfii_pi2_address1_w;
|
||||
wire csrbank1_dfii_pi2_address0_re;
|
||||
wire [7:0] csrbank1_dfii_pi2_address0_r;
|
||||
wire [13:0] csrbank1_dfii_pi2_address0_r;
|
||||
wire csrbank1_dfii_pi2_address0_we;
|
||||
wire [7:0] csrbank1_dfii_pi2_address0_w;
|
||||
wire [13:0] csrbank1_dfii_pi2_address0_w;
|
||||
wire csrbank1_dfii_pi2_baddress0_re;
|
||||
wire [2:0] csrbank1_dfii_pi2_baddress0_r;
|
||||
wire csrbank1_dfii_pi2_baddress0_we;
|
||||
wire [2:0] csrbank1_dfii_pi2_baddress0_w;
|
||||
wire csrbank1_dfii_pi2_wrdata3_re;
|
||||
wire [7:0] csrbank1_dfii_pi2_wrdata3_r;
|
||||
wire csrbank1_dfii_pi2_wrdata3_we;
|
||||
wire [7:0] csrbank1_dfii_pi2_wrdata3_w;
|
||||
wire csrbank1_dfii_pi2_wrdata2_re;
|
||||
wire [7:0] csrbank1_dfii_pi2_wrdata2_r;
|
||||
wire csrbank1_dfii_pi2_wrdata2_we;
|
||||
wire [7:0] csrbank1_dfii_pi2_wrdata2_w;
|
||||
wire csrbank1_dfii_pi2_wrdata1_re;
|
||||
wire [7:0] csrbank1_dfii_pi2_wrdata1_r;
|
||||
wire csrbank1_dfii_pi2_wrdata1_we;
|
||||
wire [7:0] csrbank1_dfii_pi2_wrdata1_w;
|
||||
wire csrbank1_dfii_pi2_wrdata0_re;
|
||||
wire [7:0] csrbank1_dfii_pi2_wrdata0_r;
|
||||
wire [31:0] csrbank1_dfii_pi2_wrdata0_r;
|
||||
wire csrbank1_dfii_pi2_wrdata0_we;
|
||||
wire [7:0] csrbank1_dfii_pi2_wrdata0_w;
|
||||
wire csrbank1_dfii_pi2_rddata3_re;
|
||||
wire [7:0] csrbank1_dfii_pi2_rddata3_r;
|
||||
wire csrbank1_dfii_pi2_rddata3_we;
|
||||
wire [7:0] csrbank1_dfii_pi2_rddata3_w;
|
||||
wire csrbank1_dfii_pi2_rddata2_re;
|
||||
wire [7:0] csrbank1_dfii_pi2_rddata2_r;
|
||||
wire csrbank1_dfii_pi2_rddata2_we;
|
||||
wire [7:0] csrbank1_dfii_pi2_rddata2_w;
|
||||
wire csrbank1_dfii_pi2_rddata1_re;
|
||||
wire [7:0] csrbank1_dfii_pi2_rddata1_r;
|
||||
wire csrbank1_dfii_pi2_rddata1_we;
|
||||
wire [7:0] csrbank1_dfii_pi2_rddata1_w;
|
||||
wire csrbank1_dfii_pi2_rddata0_re;
|
||||
wire [7:0] csrbank1_dfii_pi2_rddata0_r;
|
||||
wire csrbank1_dfii_pi2_rddata0_we;
|
||||
wire [7:0] csrbank1_dfii_pi2_rddata0_w;
|
||||
wire [31:0] csrbank1_dfii_pi2_wrdata0_w;
|
||||
wire csrbank1_dfii_pi2_rddata_re;
|
||||
wire [31:0] csrbank1_dfii_pi2_rddata_r;
|
||||
wire csrbank1_dfii_pi2_rddata_we;
|
||||
wire [31:0] csrbank1_dfii_pi2_rddata_w;
|
||||
wire csrbank1_dfii_pi3_command0_re;
|
||||
wire [5:0] csrbank1_dfii_pi3_command0_r;
|
||||
wire csrbank1_dfii_pi3_command0_we;
|
||||
wire [5:0] csrbank1_dfii_pi3_command0_w;
|
||||
wire csrbank1_dfii_pi3_address1_re;
|
||||
wire [5:0] csrbank1_dfii_pi3_address1_r;
|
||||
wire csrbank1_dfii_pi3_address1_we;
|
||||
wire [5:0] csrbank1_dfii_pi3_address1_w;
|
||||
wire csrbank1_dfii_pi3_address0_re;
|
||||
wire [7:0] csrbank1_dfii_pi3_address0_r;
|
||||
wire [13:0] csrbank1_dfii_pi3_address0_r;
|
||||
wire csrbank1_dfii_pi3_address0_we;
|
||||
wire [7:0] csrbank1_dfii_pi3_address0_w;
|
||||
wire [13:0] csrbank1_dfii_pi3_address0_w;
|
||||
wire csrbank1_dfii_pi3_baddress0_re;
|
||||
wire [2:0] csrbank1_dfii_pi3_baddress0_r;
|
||||
wire csrbank1_dfii_pi3_baddress0_we;
|
||||
wire [2:0] csrbank1_dfii_pi3_baddress0_w;
|
||||
wire csrbank1_dfii_pi3_wrdata3_re;
|
||||
wire [7:0] csrbank1_dfii_pi3_wrdata3_r;
|
||||
wire csrbank1_dfii_pi3_wrdata3_we;
|
||||
wire [7:0] csrbank1_dfii_pi3_wrdata3_w;
|
||||
wire csrbank1_dfii_pi3_wrdata2_re;
|
||||
wire [7:0] csrbank1_dfii_pi3_wrdata2_r;
|
||||
wire csrbank1_dfii_pi3_wrdata2_we;
|
||||
wire [7:0] csrbank1_dfii_pi3_wrdata2_w;
|
||||
wire csrbank1_dfii_pi3_wrdata1_re;
|
||||
wire [7:0] csrbank1_dfii_pi3_wrdata1_r;
|
||||
wire csrbank1_dfii_pi3_wrdata1_we;
|
||||
wire [7:0] csrbank1_dfii_pi3_wrdata1_w;
|
||||
wire csrbank1_dfii_pi3_wrdata0_re;
|
||||
wire [7:0] csrbank1_dfii_pi3_wrdata0_r;
|
||||
wire [31:0] csrbank1_dfii_pi3_wrdata0_r;
|
||||
wire csrbank1_dfii_pi3_wrdata0_we;
|
||||
wire [7:0] csrbank1_dfii_pi3_wrdata0_w;
|
||||
wire csrbank1_dfii_pi3_rddata3_re;
|
||||
wire [7:0] csrbank1_dfii_pi3_rddata3_r;
|
||||
wire csrbank1_dfii_pi3_rddata3_we;
|
||||
wire [7:0] csrbank1_dfii_pi3_rddata3_w;
|
||||
wire csrbank1_dfii_pi3_rddata2_re;
|
||||
wire [7:0] csrbank1_dfii_pi3_rddata2_r;
|
||||
wire csrbank1_dfii_pi3_rddata2_we;
|
||||
wire [7:0] csrbank1_dfii_pi3_rddata2_w;
|
||||
wire csrbank1_dfii_pi3_rddata1_re;
|
||||
wire [7:0] csrbank1_dfii_pi3_rddata1_r;
|
||||
wire csrbank1_dfii_pi3_rddata1_we;
|
||||
wire [7:0] csrbank1_dfii_pi3_rddata1_w;
|
||||
wire csrbank1_dfii_pi3_rddata0_re;
|
||||
wire [7:0] csrbank1_dfii_pi3_rddata0_r;
|
||||
wire csrbank1_dfii_pi3_rddata0_we;
|
||||
wire [7:0] csrbank1_dfii_pi3_rddata0_w;
|
||||
wire [31:0] csrbank1_dfii_pi3_wrdata0_w;
|
||||
wire csrbank1_dfii_pi3_rddata_re;
|
||||
wire [31:0] csrbank1_dfii_pi3_rddata_r;
|
||||
wire csrbank1_dfii_pi3_rddata_we;
|
||||
wire [31:0] csrbank1_dfii_pi3_rddata_w;
|
||||
wire csrbank1_sel;
|
||||
wire [13:0] adr;
|
||||
wire we;
|
||||
wire [7:0] dat_w;
|
||||
wire [7:0] dat_r;
|
||||
wire [31:0] dat_w;
|
||||
wire [31:0] dat_r;
|
||||
wire [24:0] slice_proxy0;
|
||||
wire [24:0] slice_proxy1;
|
||||
wire [24:0] slice_proxy2;
|
||||
@@ -9892,217 +9780,105 @@ assign csrbank0_init_done0_w = init_done_storage;
|
||||
assign csrbank0_init_error0_w = init_error_storage;
|
||||
assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
|
||||
assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0];
|
||||
assign csrbank1_dfii_control0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 1'd0));
|
||||
assign csrbank1_dfii_control0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 1'd0));
|
||||
assign csrbank1_dfii_control0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 1'd0));
|
||||
assign csrbank1_dfii_control0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 1'd0));
|
||||
assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[5:0];
|
||||
assign csrbank1_dfii_pi0_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 1'd1));
|
||||
assign csrbank1_dfii_pi0_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 1'd1));
|
||||
assign csrbank1_dfii_pi0_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 1'd1));
|
||||
assign csrbank1_dfii_pi0_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 1'd1));
|
||||
assign litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0];
|
||||
assign litedramcore_phaseinjector0_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 2'd2));
|
||||
assign litedramcore_phaseinjector0_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 2'd2));
|
||||
assign csrbank1_dfii_pi0_address1_r = interface1_bank_bus_dat_w[5:0];
|
||||
assign csrbank1_dfii_pi0_address1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 2'd3));
|
||||
assign csrbank1_dfii_pi0_address1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 2'd3));
|
||||
assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi0_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 3'd4));
|
||||
assign csrbank1_dfii_pi0_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 3'd4));
|
||||
assign litedramcore_phaseinjector0_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 2'd2));
|
||||
assign litedramcore_phaseinjector0_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 2'd2));
|
||||
assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[13:0];
|
||||
assign csrbank1_dfii_pi0_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 2'd3));
|
||||
assign csrbank1_dfii_pi0_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 2'd3));
|
||||
assign csrbank1_dfii_pi0_baddress0_r = interface1_bank_bus_dat_w[2:0];
|
||||
assign csrbank1_dfii_pi0_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 3'd5));
|
||||
assign csrbank1_dfii_pi0_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 3'd5));
|
||||
assign csrbank1_dfii_pi0_wrdata3_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi0_wrdata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 3'd6));
|
||||
assign csrbank1_dfii_pi0_wrdata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 3'd6));
|
||||
assign csrbank1_dfii_pi0_wrdata2_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi0_wrdata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 3'd7));
|
||||
assign csrbank1_dfii_pi0_wrdata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 3'd7));
|
||||
assign csrbank1_dfii_pi0_wrdata1_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi0_wrdata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd8));
|
||||
assign csrbank1_dfii_pi0_wrdata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd8));
|
||||
assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi0_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd9));
|
||||
assign csrbank1_dfii_pi0_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd9));
|
||||
assign csrbank1_dfii_pi0_rddata3_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi0_rddata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd10));
|
||||
assign csrbank1_dfii_pi0_rddata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd10));
|
||||
assign csrbank1_dfii_pi0_rddata2_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi0_rddata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd11));
|
||||
assign csrbank1_dfii_pi0_rddata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd11));
|
||||
assign csrbank1_dfii_pi0_rddata1_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi0_rddata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd12));
|
||||
assign csrbank1_dfii_pi0_rddata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd12));
|
||||
assign csrbank1_dfii_pi0_rddata0_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi0_rddata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd13));
|
||||
assign csrbank1_dfii_pi0_rddata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd13));
|
||||
assign csrbank1_dfii_pi0_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd4));
|
||||
assign csrbank1_dfii_pi0_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd4));
|
||||
assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[31:0];
|
||||
assign csrbank1_dfii_pi0_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd5));
|
||||
assign csrbank1_dfii_pi0_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd5));
|
||||
assign csrbank1_dfii_pi0_rddata_r = interface1_bank_bus_dat_w[31:0];
|
||||
assign csrbank1_dfii_pi0_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd6));
|
||||
assign csrbank1_dfii_pi0_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd6));
|
||||
assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[5:0];
|
||||
assign csrbank1_dfii_pi1_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd14));
|
||||
assign csrbank1_dfii_pi1_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd14));
|
||||
assign csrbank1_dfii_pi1_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd7));
|
||||
assign csrbank1_dfii_pi1_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd7));
|
||||
assign litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0];
|
||||
assign litedramcore_phaseinjector1_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd15));
|
||||
assign litedramcore_phaseinjector1_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd15));
|
||||
assign csrbank1_dfii_pi1_address1_r = interface1_bank_bus_dat_w[5:0];
|
||||
assign csrbank1_dfii_pi1_address1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd16));
|
||||
assign csrbank1_dfii_pi1_address1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd16));
|
||||
assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi1_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd17));
|
||||
assign csrbank1_dfii_pi1_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd17));
|
||||
assign litedramcore_phaseinjector1_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd8));
|
||||
assign litedramcore_phaseinjector1_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd8));
|
||||
assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[13:0];
|
||||
assign csrbank1_dfii_pi1_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd9));
|
||||
assign csrbank1_dfii_pi1_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd9));
|
||||
assign csrbank1_dfii_pi1_baddress0_r = interface1_bank_bus_dat_w[2:0];
|
||||
assign csrbank1_dfii_pi1_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd18));
|
||||
assign csrbank1_dfii_pi1_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd18));
|
||||
assign csrbank1_dfii_pi1_wrdata3_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi1_wrdata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd19));
|
||||
assign csrbank1_dfii_pi1_wrdata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd19));
|
||||
assign csrbank1_dfii_pi1_wrdata2_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi1_wrdata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd20));
|
||||
assign csrbank1_dfii_pi1_wrdata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd20));
|
||||
assign csrbank1_dfii_pi1_wrdata1_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi1_wrdata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd21));
|
||||
assign csrbank1_dfii_pi1_wrdata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd21));
|
||||
assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi1_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd22));
|
||||
assign csrbank1_dfii_pi1_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd22));
|
||||
assign csrbank1_dfii_pi1_rddata3_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi1_rddata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd23));
|
||||
assign csrbank1_dfii_pi1_rddata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd23));
|
||||
assign csrbank1_dfii_pi1_rddata2_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi1_rddata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd24));
|
||||
assign csrbank1_dfii_pi1_rddata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd24));
|
||||
assign csrbank1_dfii_pi1_rddata1_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi1_rddata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd25));
|
||||
assign csrbank1_dfii_pi1_rddata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd25));
|
||||
assign csrbank1_dfii_pi1_rddata0_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi1_rddata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd26));
|
||||
assign csrbank1_dfii_pi1_rddata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd26));
|
||||
assign csrbank1_dfii_pi1_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd10));
|
||||
assign csrbank1_dfii_pi1_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd10));
|
||||
assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[31:0];
|
||||
assign csrbank1_dfii_pi1_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd11));
|
||||
assign csrbank1_dfii_pi1_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd11));
|
||||
assign csrbank1_dfii_pi1_rddata_r = interface1_bank_bus_dat_w[31:0];
|
||||
assign csrbank1_dfii_pi1_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd12));
|
||||
assign csrbank1_dfii_pi1_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd12));
|
||||
assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[5:0];
|
||||
assign csrbank1_dfii_pi2_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd27));
|
||||
assign csrbank1_dfii_pi2_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd27));
|
||||
assign csrbank1_dfii_pi2_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd13));
|
||||
assign csrbank1_dfii_pi2_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd13));
|
||||
assign litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0];
|
||||
assign litedramcore_phaseinjector2_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd28));
|
||||
assign litedramcore_phaseinjector2_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd28));
|
||||
assign csrbank1_dfii_pi2_address1_r = interface1_bank_bus_dat_w[5:0];
|
||||
assign csrbank1_dfii_pi2_address1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd29));
|
||||
assign csrbank1_dfii_pi2_address1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd29));
|
||||
assign csrbank1_dfii_pi2_address0_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi2_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd30));
|
||||
assign csrbank1_dfii_pi2_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd30));
|
||||
assign litedramcore_phaseinjector2_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd14));
|
||||
assign litedramcore_phaseinjector2_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd14));
|
||||
assign csrbank1_dfii_pi2_address0_r = interface1_bank_bus_dat_w[13:0];
|
||||
assign csrbank1_dfii_pi2_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd15));
|
||||
assign csrbank1_dfii_pi2_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd15));
|
||||
assign csrbank1_dfii_pi2_baddress0_r = interface1_bank_bus_dat_w[2:0];
|
||||
assign csrbank1_dfii_pi2_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd31));
|
||||
assign csrbank1_dfii_pi2_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd31));
|
||||
assign csrbank1_dfii_pi2_wrdata3_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi2_wrdata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd32));
|
||||
assign csrbank1_dfii_pi2_wrdata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd32));
|
||||
assign csrbank1_dfii_pi2_wrdata2_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi2_wrdata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd33));
|
||||
assign csrbank1_dfii_pi2_wrdata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd33));
|
||||
assign csrbank1_dfii_pi2_wrdata1_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi2_wrdata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd34));
|
||||
assign csrbank1_dfii_pi2_wrdata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd34));
|
||||
assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi2_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd35));
|
||||
assign csrbank1_dfii_pi2_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd35));
|
||||
assign csrbank1_dfii_pi2_rddata3_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi2_rddata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd36));
|
||||
assign csrbank1_dfii_pi2_rddata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd36));
|
||||
assign csrbank1_dfii_pi2_rddata2_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi2_rddata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd37));
|
||||
assign csrbank1_dfii_pi2_rddata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd37));
|
||||
assign csrbank1_dfii_pi2_rddata1_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi2_rddata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd38));
|
||||
assign csrbank1_dfii_pi2_rddata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd38));
|
||||
assign csrbank1_dfii_pi2_rddata0_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi2_rddata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd39));
|
||||
assign csrbank1_dfii_pi2_rddata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd39));
|
||||
assign csrbank1_dfii_pi2_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd16));
|
||||
assign csrbank1_dfii_pi2_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd16));
|
||||
assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[31:0];
|
||||
assign csrbank1_dfii_pi2_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd17));
|
||||
assign csrbank1_dfii_pi2_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd17));
|
||||
assign csrbank1_dfii_pi2_rddata_r = interface1_bank_bus_dat_w[31:0];
|
||||
assign csrbank1_dfii_pi2_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd18));
|
||||
assign csrbank1_dfii_pi2_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd18));
|
||||
assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[5:0];
|
||||
assign csrbank1_dfii_pi3_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd40));
|
||||
assign csrbank1_dfii_pi3_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd40));
|
||||
assign csrbank1_dfii_pi3_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd19));
|
||||
assign csrbank1_dfii_pi3_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd19));
|
||||
assign litedramcore_phaseinjector3_command_issue_r = interface1_bank_bus_dat_w[0];
|
||||
assign litedramcore_phaseinjector3_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd41));
|
||||
assign litedramcore_phaseinjector3_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd41));
|
||||
assign csrbank1_dfii_pi3_address1_r = interface1_bank_bus_dat_w[5:0];
|
||||
assign csrbank1_dfii_pi3_address1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd42));
|
||||
assign csrbank1_dfii_pi3_address1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd42));
|
||||
assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi3_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd43));
|
||||
assign csrbank1_dfii_pi3_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd43));
|
||||
assign litedramcore_phaseinjector3_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd20));
|
||||
assign litedramcore_phaseinjector3_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd20));
|
||||
assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[13:0];
|
||||
assign csrbank1_dfii_pi3_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd21));
|
||||
assign csrbank1_dfii_pi3_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd21));
|
||||
assign csrbank1_dfii_pi3_baddress0_r = interface1_bank_bus_dat_w[2:0];
|
||||
assign csrbank1_dfii_pi3_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd44));
|
||||
assign csrbank1_dfii_pi3_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd44));
|
||||
assign csrbank1_dfii_pi3_wrdata3_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi3_wrdata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd45));
|
||||
assign csrbank1_dfii_pi3_wrdata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd45));
|
||||
assign csrbank1_dfii_pi3_wrdata2_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi3_wrdata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd46));
|
||||
assign csrbank1_dfii_pi3_wrdata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd46));
|
||||
assign csrbank1_dfii_pi3_wrdata1_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi3_wrdata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd47));
|
||||
assign csrbank1_dfii_pi3_wrdata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd47));
|
||||
assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi3_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd48));
|
||||
assign csrbank1_dfii_pi3_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd48));
|
||||
assign csrbank1_dfii_pi3_rddata3_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi3_rddata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd49));
|
||||
assign csrbank1_dfii_pi3_rddata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd49));
|
||||
assign csrbank1_dfii_pi3_rddata2_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi3_rddata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd50));
|
||||
assign csrbank1_dfii_pi3_rddata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd50));
|
||||
assign csrbank1_dfii_pi3_rddata1_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi3_rddata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd51));
|
||||
assign csrbank1_dfii_pi3_rddata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd51));
|
||||
assign csrbank1_dfii_pi3_rddata0_r = interface1_bank_bus_dat_w[7:0];
|
||||
assign csrbank1_dfii_pi3_rddata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd52));
|
||||
assign csrbank1_dfii_pi3_rddata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd52));
|
||||
assign csrbank1_dfii_pi3_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd22));
|
||||
assign csrbank1_dfii_pi3_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd22));
|
||||
assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[31:0];
|
||||
assign csrbank1_dfii_pi3_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd23));
|
||||
assign csrbank1_dfii_pi3_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd23));
|
||||
assign csrbank1_dfii_pi3_rddata_r = interface1_bank_bus_dat_w[31:0];
|
||||
assign csrbank1_dfii_pi3_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd24));
|
||||
assign csrbank1_dfii_pi3_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd24));
|
||||
assign csrbank1_dfii_control0_w = litedramcore_storage[3:0];
|
||||
assign csrbank1_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
|
||||
assign csrbank1_dfii_pi0_address1_w = litedramcore_phaseinjector0_address_storage[13:8];
|
||||
assign csrbank1_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[7:0];
|
||||
assign csrbank1_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[13:0];
|
||||
assign csrbank1_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
|
||||
assign csrbank1_dfii_pi0_wrdata3_w = litedramcore_phaseinjector0_wrdata_storage[31:24];
|
||||
assign csrbank1_dfii_pi0_wrdata2_w = litedramcore_phaseinjector0_wrdata_storage[23:16];
|
||||
assign csrbank1_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[15:8];
|
||||
assign csrbank1_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[7:0];
|
||||
assign csrbank1_dfii_pi0_rddata3_w = litedramcore_phaseinjector0_status[31:24];
|
||||
assign csrbank1_dfii_pi0_rddata2_w = litedramcore_phaseinjector0_status[23:16];
|
||||
assign csrbank1_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_status[15:8];
|
||||
assign csrbank1_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_status[7:0];
|
||||
assign litedramcore_phaseinjector0_we = csrbank1_dfii_pi0_rddata0_we;
|
||||
assign csrbank1_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0];
|
||||
assign csrbank1_dfii_pi0_rddata_w = litedramcore_phaseinjector0_status[31:0];
|
||||
assign litedramcore_phaseinjector0_we = csrbank1_dfii_pi0_rddata_we;
|
||||
assign csrbank1_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
|
||||
assign csrbank1_dfii_pi1_address1_w = litedramcore_phaseinjector1_address_storage[13:8];
|
||||
assign csrbank1_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[7:0];
|
||||
assign csrbank1_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[13:0];
|
||||
assign csrbank1_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
|
||||
assign csrbank1_dfii_pi1_wrdata3_w = litedramcore_phaseinjector1_wrdata_storage[31:24];
|
||||
assign csrbank1_dfii_pi1_wrdata2_w = litedramcore_phaseinjector1_wrdata_storage[23:16];
|
||||
assign csrbank1_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[15:8];
|
||||
assign csrbank1_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[7:0];
|
||||
assign csrbank1_dfii_pi1_rddata3_w = litedramcore_phaseinjector1_status[31:24];
|
||||
assign csrbank1_dfii_pi1_rddata2_w = litedramcore_phaseinjector1_status[23:16];
|
||||
assign csrbank1_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_status[15:8];
|
||||
assign csrbank1_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_status[7:0];
|
||||
assign litedramcore_phaseinjector1_we = csrbank1_dfii_pi1_rddata0_we;
|
||||
assign csrbank1_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0];
|
||||
assign csrbank1_dfii_pi1_rddata_w = litedramcore_phaseinjector1_status[31:0];
|
||||
assign litedramcore_phaseinjector1_we = csrbank1_dfii_pi1_rddata_we;
|
||||
assign csrbank1_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0];
|
||||
assign csrbank1_dfii_pi2_address1_w = litedramcore_phaseinjector2_address_storage[13:8];
|
||||
assign csrbank1_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[7:0];
|
||||
assign csrbank1_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[13:0];
|
||||
assign csrbank1_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0];
|
||||
assign csrbank1_dfii_pi2_wrdata3_w = litedramcore_phaseinjector2_wrdata_storage[31:24];
|
||||
assign csrbank1_dfii_pi2_wrdata2_w = litedramcore_phaseinjector2_wrdata_storage[23:16];
|
||||
assign csrbank1_dfii_pi2_wrdata1_w = litedramcore_phaseinjector2_wrdata_storage[15:8];
|
||||
assign csrbank1_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[7:0];
|
||||
assign csrbank1_dfii_pi2_rddata3_w = litedramcore_phaseinjector2_status[31:24];
|
||||
assign csrbank1_dfii_pi2_rddata2_w = litedramcore_phaseinjector2_status[23:16];
|
||||
assign csrbank1_dfii_pi2_rddata1_w = litedramcore_phaseinjector2_status[15:8];
|
||||
assign csrbank1_dfii_pi2_rddata0_w = litedramcore_phaseinjector2_status[7:0];
|
||||
assign litedramcore_phaseinjector2_we = csrbank1_dfii_pi2_rddata0_we;
|
||||
assign csrbank1_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0];
|
||||
assign csrbank1_dfii_pi2_rddata_w = litedramcore_phaseinjector2_status[31:0];
|
||||
assign litedramcore_phaseinjector2_we = csrbank1_dfii_pi2_rddata_we;
|
||||
assign csrbank1_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0];
|
||||
assign csrbank1_dfii_pi3_address1_w = litedramcore_phaseinjector3_address_storage[13:8];
|
||||
assign csrbank1_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[7:0];
|
||||
assign csrbank1_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[13:0];
|
||||
assign csrbank1_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0];
|
||||
assign csrbank1_dfii_pi3_wrdata3_w = litedramcore_phaseinjector3_wrdata_storage[31:24];
|
||||
assign csrbank1_dfii_pi3_wrdata2_w = litedramcore_phaseinjector3_wrdata_storage[23:16];
|
||||
assign csrbank1_dfii_pi3_wrdata1_w = litedramcore_phaseinjector3_wrdata_storage[15:8];
|
||||
assign csrbank1_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[7:0];
|
||||
assign csrbank1_dfii_pi3_rddata3_w = litedramcore_phaseinjector3_status[31:24];
|
||||
assign csrbank1_dfii_pi3_rddata2_w = litedramcore_phaseinjector3_status[23:16];
|
||||
assign csrbank1_dfii_pi3_rddata1_w = litedramcore_phaseinjector3_status[15:8];
|
||||
assign csrbank1_dfii_pi3_rddata0_w = litedramcore_phaseinjector3_status[7:0];
|
||||
assign litedramcore_phaseinjector3_we = csrbank1_dfii_pi3_rddata0_we;
|
||||
assign csrbank1_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0];
|
||||
assign csrbank1_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0];
|
||||
assign litedramcore_phaseinjector3_we = csrbank1_dfii_pi3_rddata_we;
|
||||
assign adr = litedramcore_adr;
|
||||
assign we = litedramcore_we;
|
||||
assign dat_w = litedramcore_dat_w;
|
||||
@@ -12768,7 +12544,7 @@ always @(posedge sys_clk) begin
|
||||
init_error_re <= csrbank0_init_error0_re;
|
||||
interface1_bank_bus_dat_r <= 1'd0;
|
||||
if (csrbank1_sel) begin
|
||||
case (interface1_bank_bus_adr[5:0])
|
||||
case (interface1_bank_bus_adr[4:0])
|
||||
1'd0: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_control0_w;
|
||||
end
|
||||
@@ -12779,154 +12555,70 @@ always @(posedge sys_clk) begin
|
||||
interface1_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
|
||||
end
|
||||
2'd3: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address1_w;
|
||||
end
|
||||
3'd4: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address0_w;
|
||||
end
|
||||
3'd5: begin
|
||||
3'd4: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_baddress0_w;
|
||||
end
|
||||
3'd6: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata3_w;
|
||||
end
|
||||
3'd7: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata2_w;
|
||||
end
|
||||
4'd8: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata1_w;
|
||||
end
|
||||
4'd9: begin
|
||||
3'd5: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata0_w;
|
||||
end
|
||||
4'd10: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata3_w;
|
||||
3'd6: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata_w;
|
||||
end
|
||||
4'd11: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata2_w;
|
||||
end
|
||||
4'd12: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata1_w;
|
||||
end
|
||||
4'd13: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata0_w;
|
||||
end
|
||||
4'd14: begin
|
||||
3'd7: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_command0_w;
|
||||
end
|
||||
4'd15: begin
|
||||
4'd8: begin
|
||||
interface1_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
|
||||
end
|
||||
5'd16: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address1_w;
|
||||
end
|
||||
5'd17: begin
|
||||
4'd9: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address0_w;
|
||||
end
|
||||
5'd18: begin
|
||||
4'd10: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_baddress0_w;
|
||||
end
|
||||
5'd19: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata3_w;
|
||||
end
|
||||
5'd20: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata2_w;
|
||||
end
|
||||
5'd21: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata1_w;
|
||||
end
|
||||
5'd22: begin
|
||||
4'd11: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata0_w;
|
||||
end
|
||||
5'd23: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata3_w;
|
||||
4'd12: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata_w;
|
||||
end
|
||||
5'd24: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata2_w;
|
||||
end
|
||||
5'd25: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata1_w;
|
||||
end
|
||||
5'd26: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata0_w;
|
||||
end
|
||||
5'd27: begin
|
||||
4'd13: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_command0_w;
|
||||
end
|
||||
5'd28: begin
|
||||
4'd14: begin
|
||||
interface1_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
|
||||
end
|
||||
5'd29: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address1_w;
|
||||
end
|
||||
5'd30: begin
|
||||
4'd15: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address0_w;
|
||||
end
|
||||
5'd31: begin
|
||||
5'd16: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_baddress0_w;
|
||||
end
|
||||
6'd32: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata3_w;
|
||||
end
|
||||
6'd33: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata2_w;
|
||||
end
|
||||
6'd34: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata1_w;
|
||||
end
|
||||
6'd35: begin
|
||||
5'd17: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata0_w;
|
||||
end
|
||||
6'd36: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata3_w;
|
||||
5'd18: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata_w;
|
||||
end
|
||||
6'd37: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata2_w;
|
||||
end
|
||||
6'd38: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata1_w;
|
||||
end
|
||||
6'd39: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata0_w;
|
||||
end
|
||||
6'd40: begin
|
||||
5'd19: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_command0_w;
|
||||
end
|
||||
6'd41: begin
|
||||
5'd20: begin
|
||||
interface1_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
|
||||
end
|
||||
6'd42: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address1_w;
|
||||
end
|
||||
6'd43: begin
|
||||
5'd21: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address0_w;
|
||||
end
|
||||
6'd44: begin
|
||||
5'd22: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_baddress0_w;
|
||||
end
|
||||
6'd45: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata3_w;
|
||||
end
|
||||
6'd46: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata2_w;
|
||||
end
|
||||
6'd47: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata1_w;
|
||||
end
|
||||
6'd48: begin
|
||||
5'd23: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata0_w;
|
||||
end
|
||||
6'd49: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata3_w;
|
||||
end
|
||||
6'd50: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata2_w;
|
||||
end
|
||||
6'd51: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata1_w;
|
||||
end
|
||||
6'd52: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata0_w;
|
||||
5'd24: begin
|
||||
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata_w;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
@@ -12938,112 +12630,64 @@ always @(posedge sys_clk) begin
|
||||
litedramcore_phaseinjector0_command_storage[5:0] <= csrbank1_dfii_pi0_command0_r;
|
||||
end
|
||||
litedramcore_phaseinjector0_command_re <= csrbank1_dfii_pi0_command0_re;
|
||||
if (csrbank1_dfii_pi0_address1_re) begin
|
||||
litedramcore_phaseinjector0_address_storage[13:8] <= csrbank1_dfii_pi0_address1_r;
|
||||
end
|
||||
if (csrbank1_dfii_pi0_address0_re) begin
|
||||
litedramcore_phaseinjector0_address_storage[7:0] <= csrbank1_dfii_pi0_address0_r;
|
||||
litedramcore_phaseinjector0_address_storage[13:0] <= csrbank1_dfii_pi0_address0_r;
|
||||
end
|
||||
litedramcore_phaseinjector0_address_re <= csrbank1_dfii_pi0_address0_re;
|
||||
if (csrbank1_dfii_pi0_baddress0_re) begin
|
||||
litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank1_dfii_pi0_baddress0_r;
|
||||
end
|
||||
litedramcore_phaseinjector0_baddress_re <= csrbank1_dfii_pi0_baddress0_re;
|
||||
if (csrbank1_dfii_pi0_wrdata3_re) begin
|
||||
litedramcore_phaseinjector0_wrdata_storage[31:24] <= csrbank1_dfii_pi0_wrdata3_r;
|
||||
end
|
||||
if (csrbank1_dfii_pi0_wrdata2_re) begin
|
||||
litedramcore_phaseinjector0_wrdata_storage[23:16] <= csrbank1_dfii_pi0_wrdata2_r;
|
||||
end
|
||||
if (csrbank1_dfii_pi0_wrdata1_re) begin
|
||||
litedramcore_phaseinjector0_wrdata_storage[15:8] <= csrbank1_dfii_pi0_wrdata1_r;
|
||||
end
|
||||
if (csrbank1_dfii_pi0_wrdata0_re) begin
|
||||
litedramcore_phaseinjector0_wrdata_storage[7:0] <= csrbank1_dfii_pi0_wrdata0_r;
|
||||
litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank1_dfii_pi0_wrdata0_r;
|
||||
end
|
||||
litedramcore_phaseinjector0_wrdata_re <= csrbank1_dfii_pi0_wrdata0_re;
|
||||
if (csrbank1_dfii_pi1_command0_re) begin
|
||||
litedramcore_phaseinjector1_command_storage[5:0] <= csrbank1_dfii_pi1_command0_r;
|
||||
end
|
||||
litedramcore_phaseinjector1_command_re <= csrbank1_dfii_pi1_command0_re;
|
||||
if (csrbank1_dfii_pi1_address1_re) begin
|
||||
litedramcore_phaseinjector1_address_storage[13:8] <= csrbank1_dfii_pi1_address1_r;
|
||||
end
|
||||
if (csrbank1_dfii_pi1_address0_re) begin
|
||||
litedramcore_phaseinjector1_address_storage[7:0] <= csrbank1_dfii_pi1_address0_r;
|
||||
litedramcore_phaseinjector1_address_storage[13:0] <= csrbank1_dfii_pi1_address0_r;
|
||||
end
|
||||
litedramcore_phaseinjector1_address_re <= csrbank1_dfii_pi1_address0_re;
|
||||
if (csrbank1_dfii_pi1_baddress0_re) begin
|
||||
litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank1_dfii_pi1_baddress0_r;
|
||||
end
|
||||
litedramcore_phaseinjector1_baddress_re <= csrbank1_dfii_pi1_baddress0_re;
|
||||
if (csrbank1_dfii_pi1_wrdata3_re) begin
|
||||
litedramcore_phaseinjector1_wrdata_storage[31:24] <= csrbank1_dfii_pi1_wrdata3_r;
|
||||
end
|
||||
if (csrbank1_dfii_pi1_wrdata2_re) begin
|
||||
litedramcore_phaseinjector1_wrdata_storage[23:16] <= csrbank1_dfii_pi1_wrdata2_r;
|
||||
end
|
||||
if (csrbank1_dfii_pi1_wrdata1_re) begin
|
||||
litedramcore_phaseinjector1_wrdata_storage[15:8] <= csrbank1_dfii_pi1_wrdata1_r;
|
||||
end
|
||||
if (csrbank1_dfii_pi1_wrdata0_re) begin
|
||||
litedramcore_phaseinjector1_wrdata_storage[7:0] <= csrbank1_dfii_pi1_wrdata0_r;
|
||||
litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank1_dfii_pi1_wrdata0_r;
|
||||
end
|
||||
litedramcore_phaseinjector1_wrdata_re <= csrbank1_dfii_pi1_wrdata0_re;
|
||||
if (csrbank1_dfii_pi2_command0_re) begin
|
||||
litedramcore_phaseinjector2_command_storage[5:0] <= csrbank1_dfii_pi2_command0_r;
|
||||
end
|
||||
litedramcore_phaseinjector2_command_re <= csrbank1_dfii_pi2_command0_re;
|
||||
if (csrbank1_dfii_pi2_address1_re) begin
|
||||
litedramcore_phaseinjector2_address_storage[13:8] <= csrbank1_dfii_pi2_address1_r;
|
||||
end
|
||||
if (csrbank1_dfii_pi2_address0_re) begin
|
||||
litedramcore_phaseinjector2_address_storage[7:0] <= csrbank1_dfii_pi2_address0_r;
|
||||
litedramcore_phaseinjector2_address_storage[13:0] <= csrbank1_dfii_pi2_address0_r;
|
||||
end
|
||||
litedramcore_phaseinjector2_address_re <= csrbank1_dfii_pi2_address0_re;
|
||||
if (csrbank1_dfii_pi2_baddress0_re) begin
|
||||
litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank1_dfii_pi2_baddress0_r;
|
||||
end
|
||||
litedramcore_phaseinjector2_baddress_re <= csrbank1_dfii_pi2_baddress0_re;
|
||||
if (csrbank1_dfii_pi2_wrdata3_re) begin
|
||||
litedramcore_phaseinjector2_wrdata_storage[31:24] <= csrbank1_dfii_pi2_wrdata3_r;
|
||||
end
|
||||
if (csrbank1_dfii_pi2_wrdata2_re) begin
|
||||
litedramcore_phaseinjector2_wrdata_storage[23:16] <= csrbank1_dfii_pi2_wrdata2_r;
|
||||
end
|
||||
if (csrbank1_dfii_pi2_wrdata1_re) begin
|
||||
litedramcore_phaseinjector2_wrdata_storage[15:8] <= csrbank1_dfii_pi2_wrdata1_r;
|
||||
end
|
||||
if (csrbank1_dfii_pi2_wrdata0_re) begin
|
||||
litedramcore_phaseinjector2_wrdata_storage[7:0] <= csrbank1_dfii_pi2_wrdata0_r;
|
||||
litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank1_dfii_pi2_wrdata0_r;
|
||||
end
|
||||
litedramcore_phaseinjector2_wrdata_re <= csrbank1_dfii_pi2_wrdata0_re;
|
||||
if (csrbank1_dfii_pi3_command0_re) begin
|
||||
litedramcore_phaseinjector3_command_storage[5:0] <= csrbank1_dfii_pi3_command0_r;
|
||||
end
|
||||
litedramcore_phaseinjector3_command_re <= csrbank1_dfii_pi3_command0_re;
|
||||
if (csrbank1_dfii_pi3_address1_re) begin
|
||||
litedramcore_phaseinjector3_address_storage[13:8] <= csrbank1_dfii_pi3_address1_r;
|
||||
end
|
||||
if (csrbank1_dfii_pi3_address0_re) begin
|
||||
litedramcore_phaseinjector3_address_storage[7:0] <= csrbank1_dfii_pi3_address0_r;
|
||||
litedramcore_phaseinjector3_address_storage[13:0] <= csrbank1_dfii_pi3_address0_r;
|
||||
end
|
||||
litedramcore_phaseinjector3_address_re <= csrbank1_dfii_pi3_address0_re;
|
||||
if (csrbank1_dfii_pi3_baddress0_re) begin
|
||||
litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank1_dfii_pi3_baddress0_r;
|
||||
end
|
||||
litedramcore_phaseinjector3_baddress_re <= csrbank1_dfii_pi3_baddress0_re;
|
||||
if (csrbank1_dfii_pi3_wrdata3_re) begin
|
||||
litedramcore_phaseinjector3_wrdata_storage[31:24] <= csrbank1_dfii_pi3_wrdata3_r;
|
||||
end
|
||||
if (csrbank1_dfii_pi3_wrdata2_re) begin
|
||||
litedramcore_phaseinjector3_wrdata_storage[23:16] <= csrbank1_dfii_pi3_wrdata2_r;
|
||||
end
|
||||
if (csrbank1_dfii_pi3_wrdata1_re) begin
|
||||
litedramcore_phaseinjector3_wrdata_storage[15:8] <= csrbank1_dfii_pi3_wrdata1_r;
|
||||
end
|
||||
if (csrbank1_dfii_pi3_wrdata0_re) begin
|
||||
litedramcore_phaseinjector3_wrdata_storage[7:0] <= csrbank1_dfii_pi3_wrdata0_r;
|
||||
litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank1_dfii_pi3_wrdata0_r;
|
||||
end
|
||||
litedramcore_phaseinjector3_wrdata_re <= csrbank1_dfii_pi3_wrdata0_re;
|
||||
if (sys_rst) begin
|
||||
|
||||
Reference in New Issue
Block a user