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https://github.com/antonblanchard/microwatt.git
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Metavalue cleanup for decoder1.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
This commit is contained in:
Michael Neuling
parent
7656abd765
commit
602ba25c70
100
decode1.vhdl
100
decode1.vhdl
@ -36,6 +36,8 @@ architecture behaviour of decode1 is
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constant illegal_inst : decode_rom_t :=
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(NONE, NONE, OP_ILLEGAL, NONE, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', NONE);
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constant x_inst : decode_rom_t :=
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(NONE, NONE, OP_ILLEGAL, NONE, NONE, NONE, NONE, 'X', 'X', 'X', 'X', ZERO, 'X', NONE, 'X', 'X', 'X', 'X', 'X', 'X', NONE, 'X', 'X', NONE);
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-- If we have an FPU, then it is used for integer divisions,
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-- otherwise a dedicated divider in the ALU is used.
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@ -664,14 +666,23 @@ begin
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br_offset := (others => '0');
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majorop := unsigned(f_in.insn(31 downto 26));
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v.decode := major_decode_rom_array(to_integer(majorop));
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if is_X(majorop) then
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v.decode := x_inst;
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else
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v.decode := major_decode_rom_array(to_integer(majorop));
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end if;
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sprn := decode_spr_num(f_in.insn);
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v.spr_info := map_spr(sprn);
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v.ram_spr := decode_ram_spr(sprn);
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if is_X(f_in.insn) then
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v.spr_info := (sel => "XXX", others => 'X');
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v.ram_spr := (index => (others => 'X'), others => 'X');
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else
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sprn := decode_spr_num(f_in.insn);
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v.spr_info := map_spr(sprn);
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v.ram_spr := decode_ram_spr(sprn);
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end if;
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case to_integer(unsigned(majorop)) is
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when 4 =>
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case unsigned(majorop) is
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when "000100" => -- 4
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-- major opcode 4, mostly VMX/VSX stuff but also some integer ops (madd*)
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minor4op := f_in.insn(5 downto 0) & f_in.insn(10 downto 6);
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vi.override := not decode_op_4_valid(to_integer(unsigned(minor4op)));
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@ -679,13 +690,17 @@ begin
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in3rc := '1';
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may_read_rb := '1';
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when 23 =>
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when "010111" => -- 23
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-- rlwnm[.]
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may_read_rb := '1';
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when 31 =>
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when "011111" => -- 31
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-- major opcode 31, lots of things
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v.decode := decode_op_31_array(to_integer(unsigned(f_in.insn(10 downto 1))));
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if is_X(f_in.insn) then
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v.decode := x_inst;
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else
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v.decode := decode_op_31_array(to_integer(unsigned(f_in.insn(10 downto 1))));
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end if;
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may_read_rb := '1';
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if std_match(f_in.insn(10 downto 1), "01-1010011") then
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@ -705,28 +720,43 @@ begin
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end if;
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when others =>
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end case;
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-- FIXME: This is a bit fragile doing this here but sprn depends
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-- on f_in.insn
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if is_X(f_in.insn) then
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vi.override_decode.unit := NONE;
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vi.override_unit := 'X';
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vi.force_single := 'X';
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end if;
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end if;
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if HAS_FPU and std_match(f_in.insn(10 downto 1), "1----10111") then
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-- lower half of column 23 has FP loads and stores
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fprs := '1';
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end if;
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when 16 =>
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when "010000" => -- 16
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-- Predict backward branches as taken, forward as untaken
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v.br_pred := f_in.insn(15);
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br_offset := resize(signed(f_in.insn(15 downto 2)), 24);
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when 18 =>
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when "010010" => -- 18
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-- Unconditional branches are always taken
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v.br_pred := '1';
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br_offset := signed(f_in.insn(25 downto 2));
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when 19 =>
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vi.override := not decode_op_19_valid(to_integer(unsigned(f_in.insn(5 downto 1) & f_in.insn(10 downto 6))));
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when "010011" => -- 19
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if is_X(f_in.insn) then
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vi.override := 'X';
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else
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vi.override := not decode_op_19_valid(to_integer(unsigned(f_in.insn(5 downto 1) & f_in.insn(10 downto 6))));
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end if;
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op_19_bits := f_in.insn(5) & f_in.insn(3) & f_in.insn(2);
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v.decode := decode_op_19_array(to_integer(unsigned(op_19_bits)));
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if is_X(op_19_bits) then
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v.decode := x_inst;
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else
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v.decode := decode_op_19_array(to_integer(unsigned(op_19_bits)));
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end if;
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when 24 =>
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when "011000" => -- 24
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-- ori, special-case the standard NOP
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if std_match(f_in.insn, "01100000000000000000000000000000") then
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report "PPC_nop";
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@ -734,23 +764,35 @@ begin
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vi.override_decode := nop_instr;
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end if;
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when 30 =>
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v.decode := decode_op_30_array(to_integer(unsigned(f_in.insn(4 downto 1))));
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when "011110" => -- 30
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if is_X(f_in.insn) then
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v.decode := x_inst;
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else
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v.decode := decode_op_30_array(to_integer(unsigned(f_in.insn(4 downto 1))));
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end if;
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may_read_rb := f_in.insn(4);
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when 52 | 53 | 54 | 55 =>
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when "110100" | "110101" | "110110" | "110111" => -- 52, 53, 54, 55
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-- stfd[u] and stfs[u]
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if HAS_FPU then
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fprs := '1';
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end if;
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when 58 =>
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v.decode := decode_op_58_array(to_integer(unsigned(f_in.insn(1 downto 0))));
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when "111010" => -- 58
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if is_X(f_in.insn) then
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v.decode := x_inst;
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else
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v.decode := decode_op_58_array(to_integer(unsigned(f_in.insn(1 downto 0))));
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end if;
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when 59 =>
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when "111011" => -- 59
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if HAS_FPU then
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-- floating point operations, mostly single-precision
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v.decode := decode_op_59_array(to_integer(unsigned(f_in.insn(5 downto 1))));
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if is_X(f_in.insn) then
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v.decode := x_inst;
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else
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v.decode := decode_op_59_array(to_integer(unsigned(f_in.insn(5 downto 1))));
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end if;
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if f_in.insn(5) = '0' and not std_match(f_in.insn(10 downto 1), "11-1001110") then
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vi.override := '1';
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end if;
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@ -760,13 +802,19 @@ begin
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may_read_rb := '1';
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end if;
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when 62 =>
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v.decode := decode_op_62_array(to_integer(unsigned(f_in.insn(1 downto 0))));
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when "111110" => -- 62
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if is_X(f_in.insn) then
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v.decode := x_inst;
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else
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v.decode := decode_op_62_array(to_integer(unsigned(f_in.insn(1 downto 0))));
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end if;
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when 63 =>
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when "111111" => -- 63
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if HAS_FPU then
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-- floating point operations, general and double-precision
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if f_in.insn(5) = '0' then
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if is_X(f_in.insn) then
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v.decode := x_inst;
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elsif f_in.insn(5) = '0' then
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v.decode := decode_op_63l_array(to_integer(unsigned(f_in.insn(4 downto 1) & f_in.insn(10 downto 6))));
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else
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v.decode := decode_op_63h_array(to_integer(unsigned(f_in.insn(4 downto 1))));
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