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https://github.com/antonblanchard/microwatt.git
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core: Remove HFSCR and Hypervisor Facility Unavailable interrupt logic
HFSCR is associated with the LPAR (Logical Partitioning) feature, which is not required for SFFS designs, so remove it and the associated logic. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This commit is contained in:
Paul Mackerras
parent
c5abe3c0a9
commit
63fff5e05c
15
common.vhdl
15
common.vhdl
@ -189,7 +189,6 @@ package common is
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constant SPRSEL_LOGD : spr_selector := 4x"5";
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constant SPRSEL_CFAR : spr_selector := 4x"6";
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constant SPRSEL_FSCR : spr_selector := 4x"7";
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constant SPRSEL_HFSCR : spr_selector := 4x"8";
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constant SPRSEL_HEIR : spr_selector := 4x"9";
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constant SPRSEL_CTRL : spr_selector := 4x"a";
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constant SPRSEL_DSCR : spr_selector := 4x"b";
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@ -198,17 +197,11 @@ package common is
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constant SPRSEL_DEXCR : spr_selector := 4x"e";
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constant SPRSEL_XER : spr_selector := 4x"f";
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-- FSCR and HFSCR bit numbers
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-- FSCR bit numbers
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constant FSCR_PREFIX : integer := 63 - 50;
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constant FSCR_SCV : integer := 63 - 51;
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constant FSCR_TAR : integer := 63 - 55;
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constant FSCR_DSCR : integer := 63 - 61;
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constant HFSCR_PREFIX : integer := 63 - 50;
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constant HFSCR_MSG : integer := 63 - 53;
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constant HFSCR_TAR : integer := 63 - 55;
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constant HFSCR_PMUSPR : integer := 63 - 60;
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constant HFSCR_DSCR : integer := 63 - 61;
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constant HFSCR_FP : integer := 63 - 63;
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-- FPSCR bit numbers
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constant FPSCR_FX : integer := 63 - 32;
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@ -301,11 +294,6 @@ package common is
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fscr_scv: std_ulogic;
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fscr_tar: std_ulogic;
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fscr_dscr: std_ulogic;
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hfscr_ic: std_ulogic_vector(3 downto 0);
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hfscr_pref: std_ulogic;
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hfscr_tar: std_ulogic;
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hfscr_dscr: std_ulogic;
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hfscr_fp: std_ulogic;
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heir: std_ulogic_vector(63 downto 0);
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dscr: std_ulogic_vector(24 downto 0);
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ciabr: std_ulogic_vector(63 downto 0);
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@ -317,7 +305,6 @@ package common is
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constant ctrl_t_init : ctrl_t :=
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(wait_state => '0', run => '1', xer_low => 18x"0",
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fscr_ic => x"0", fscr_pref => '1', fscr_scv => '1', fscr_tar => '1', fscr_dscr => '1',
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hfscr_ic => x"0", hfscr_pref => '1', hfscr_tar => '1', hfscr_dscr => '1', hfscr_fp => '1',
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dscr => (others => '0'),
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dexcr_pnh => aspect_bits_init, dexcr_pro => aspect_bits_init,
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hdexcr_hyp => aspect_bits_init, hdexcr_enf => aspect_bits_init,
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@ -327,9 +327,6 @@ begin
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when 5x"0e" =>
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isram := '0';
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sel := SPRSEL_FSCR;
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when 5x"0f" =>
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isram := '0';
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sel := SPRSEL_HFSCR;
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when 5x"10" =>
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isram := '0';
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sel := SPRSEL_HEIR;
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@ -490,8 +490,6 @@ architecture behaviour of decode1 is
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i.sel := SPRSEL_XER;
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when SPR_FSCR =>
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i.sel := SPRSEL_FSCR;
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when SPR_HFSCR =>
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i.sel := SPRSEL_HFSCR;
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when SPR_HEIR =>
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i.sel := SPRSEL_HEIR;
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when SPR_CTRL =>
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@ -92,8 +92,6 @@ architecture behaviour of execute1 is
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mult_32s : std_ulogic;
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write_fscr : std_ulogic;
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write_ic : std_ulogic;
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write_hfscr : std_ulogic;
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write_hic : std_ulogic;
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write_heir : std_ulogic;
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set_heir : std_ulogic;
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write_ctrl : std_ulogic;
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@ -410,18 +408,6 @@ architecture behaviour of execute1 is
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return ret;
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end;
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function assemble_hfscr(c: ctrl_t) return std_ulogic_vector is
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variable ret : std_ulogic_vector(63 downto 0);
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begin
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ret := (others => '0');
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ret(59 downto 56) := c.hfscr_ic;
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ret(HFSCR_PREFIX) := c.hfscr_pref;
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ret(HFSCR_TAR) := c.hfscr_tar;
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ret(HFSCR_DSCR) := c.hfscr_dscr;
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ret(HFSCR_FP) := c.hfscr_fp;
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return ret;
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end;
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function assemble_ctrl(c: ctrl_t; msrpr: std_ulogic) return std_ulogic_vector is
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variable ret : std_ulogic_vector(63 downto 0);
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begin
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@ -796,8 +782,6 @@ begin
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case dbg_spr_addr(3 downto 0) is
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when SPRSEL_FSCR =>
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dbg_spr_data <= assemble_fscr(ctrl);
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when SPRSEL_HFSCR =>
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dbg_spr_data <= assemble_hfscr(ctrl);
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when SPRSEL_HEIR =>
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dbg_spr_data <= ctrl.heir;
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when SPRSEL_CFAR =>
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@ -1457,8 +1441,6 @@ begin
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v.se.write_cfar := '1';
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when SPRSEL_FSCR =>
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v.se.write_fscr := '1';
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when SPRSEL_HFSCR =>
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v.se.write_hfscr := '1';
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when SPRSEL_HEIR =>
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v.se.write_heir := '1';
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when SPRSEL_CTRL =>
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@ -1548,22 +1530,15 @@ begin
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end case;
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if ex1.msr(MSR_PR) = '1' and e_in.prefixed = '1' and
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(ctrl.hfscr_pref = '0' or ctrl.fscr_pref = '0') then
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-- [Hypervisor] facility unavailable for prefixed instructions,
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ctrl.fscr_pref = '0' then
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-- Facility unavailable for prefixed instructions,
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-- which has higher priority than the alignment interrupt for
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-- misaligned prefixed instructions, which has higher priority than
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-- other [hypervisor] facility unavailable interrupts (e.g. for
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-- plfs with HFSCR[FP] = 0).
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-- other facility unavailable interrupts.
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v.exception := '1';
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v.ic := x"b";
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if ctrl.hfscr_pref = '0' then
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v.e.hv_intr := '1';
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v.e.intr_vec := 16#f80#;
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v.se.write_hic := '1';
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else
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v.e.intr_vec := 16#f60#;
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v.se.write_ic := '1';
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end if;
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v.e.intr_vec := 16#f60#;
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v.se.write_ic := '1';
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elsif misaligned = '1' then
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-- generate an alignment interrupt
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@ -1608,41 +1583,20 @@ begin
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v.se.write_ic := '1';
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elsif ex1.msr(MSR_PR) = '1' and e_in.uses_tar = '1' and
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(ctrl.hfscr_tar = '0' or ctrl.fscr_tar = '0') then
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-- [Hypervisor] facility unavailable for TAR access
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ctrl.fscr_tar = '0' then
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-- Facility unavailable for TAR access
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v.exception := '1';
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v.ic := x"8";
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if ctrl.hfscr_tar = '0' then
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v.e.hv_intr := '1';
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v.e.intr_vec := 16#f80#;
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v.se.write_hic := '1';
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else
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v.e.intr_vec := 16#f60#;
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v.se.write_ic := '1';
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end if;
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v.e.intr_vec := 16#f60#;
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v.se.write_ic := '1';
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elsif ex1.msr(MSR_PR) = '1' and e_in.uses_dscr = '1' and
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(ctrl.hfscr_dscr = '0' or ctrl.fscr_dscr = '0') then
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-- [Hypervisor] facility unavailable for DSCR access
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ctrl.fscr_dscr = '0' then
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-- Facility unavailable for DSCR access
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v.exception := '1';
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v.ic := x"2";
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if ctrl.hfscr_dscr = '0' then
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v.e.hv_intr := '1';
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v.e.intr_vec := 16#f80#;
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v.se.write_hic := '1';
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else
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v.e.intr_vec := 16#f60#;
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v.se.write_ic := '1';
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end if;
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elsif HAS_FPU and ex1.msr(MSR_PR) = '1' and e_in.fac = FPU and
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ctrl.hfscr_fp = '0' then
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-- Hypervisor facility unavailable for FP instructions
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v.exception := '1';
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v.ic := x"0";
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v.e.hv_intr := '1';
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v.e.intr_vec := 16#f80#;
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v.se.write_hic := '1';
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v.e.intr_vec := 16#f60#;
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v.se.write_ic := '1';
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elsif HAS_FPU and ex1.msr(MSR_FP) = '0' and e_in.fac = FPU then
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-- generate a floating-point unavailable interrupt
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@ -1977,7 +1931,6 @@ begin
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log_rd_data when SPRSEL_LOGD,
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ctrl.cfar when SPRSEL_CFAR,
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assemble_fscr(ctrl) when SPRSEL_FSCR,
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assemble_hfscr(ctrl) when SPRSEL_HFSCR,
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ctrl.heir when SPRSEL_HEIR,
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assemble_ctrl(ctrl, ex1.msr(MSR_PR)) when SPRSEL_CTRL,
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39x"0" & ctrl.dscr when SPRSEL_DSCR,
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@ -2127,15 +2080,6 @@ begin
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v.log_addr_spr := std_ulogic_vector(unsigned(ex2.log_addr_spr) + 1);
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end if;
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x_to_pmu.mtspr <= ex1.se.write_pmuspr;
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if ex1.se.write_hfscr = '1' then
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ctrl_tmp.hfscr_ic <= ex1.e.write_data(59 downto 56);
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ctrl_tmp.hfscr_pref <= ex1.e.write_data(HFSCR_PREFIX);
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ctrl_tmp.hfscr_tar <= ex1.e.write_data(HFSCR_TAR);
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ctrl_tmp.hfscr_dscr <= ex1.e.write_data(HFSCR_DSCR);
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ctrl_tmp.hfscr_fp <= ex1.e.write_data(HFSCR_FP);
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elsif ex1.se.write_hic = '1' then
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ctrl_tmp.hfscr_ic <= ex1.ic;
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end if;
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if ex1.se.write_fscr = '1' then
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ctrl_tmp.fscr_ic <= ex1.e.write_data(59 downto 56);
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ctrl_tmp.fscr_pref <= ex1.e.write_data(FSCR_PREFIX);
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@ -552,7 +552,7 @@ static const char *fast_spr_names[] =
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"lr", "ctr", "srr0", "srr1", "hsrr0", "hsrr1",
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"sprg0", "sprg1", "sprg2", "sprg3",
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"hsprg0", "hsprg1", "xer", "tar",
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"fscr", "hfscr", "heir", "cfar",
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"fscr", "unused", "heir", "cfar",
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};
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static const char *ldst_spr_names[] = {
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