ASIC: Switch to ghdl --synth

Use ghdl --synth to convert to verilog directly instead of going
through Yosys.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

Makefile

@@ -253,7 +253,7 @@ microwatt.v: $(synth_files) $(RAM_INIT_FILE)
 	$(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
 
 microwatt_asic.v: $(asic_synth_files)
-	$(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(asic_synth_files) -e toplevel; write_verilog $@"
+	$(GHDL) --synth --std=08 --no-formal --out=verilog $(GHDL_IMAGE_GENERICS) $(asic_synth_files) -e toplevel > $@
 
 microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
 	$(VERILATOR) $(VERILATOR_FLAGS) -CFLAGS "$(VERILATOR_CFLAGS) -DCLK_FREQUENCY=$(CLK_FREQUENCY)" -Iuart16550 --assert --cc --exe --build $^ -o $@ -top-module toplevel

caravel/insert_power.py

@@ -5,28 +5,16 @@ import re
 
 module_regex = r'[a-zA-Z0-9_:\.\\]+'
 
-# match:
-# module dcache(clk, rst, d_in, m_in, wishbone_in, d_out, m_out, stall_out, wishbone_out);
-# A bit of a hack - ignore anything contining a '`', and assume that means we've already
-# processed this module in a previous run. This helps when having to run this script
-# multiple times for different power names.
-multiline_module_re = re.compile(r'module\s+(' + module_regex + r')\(([^`]*?)\);', re.DOTALL)
-module_re = re.compile(r'module\s+(' + module_regex + r')\((.*?)\);')
+module_re = re.compile(r'module\s+(' + module_regex + r')')
 
 # match:
 # dcache_64_2_2_2_2_12_0 dcache_0 (
 hookup_re = re.compile(r'\s+(' + module_regex + r') ' + module_regex + r'\s+\(')
 
-header1 = """\
+header = """\
 `ifdef USE_POWER_PINS
-  {power}, {ground},
-`endif\
-"""
-
-header2 = """\
-`ifdef USE_POWER_PINS
-  inout {power};
-  inout {ground};
+   inout {power},
+   inout {ground},
 `endif\
 """
 
@@ -48,25 +36,23 @@ parser.add_argument('--module', required=True, action='append', help='Module to
 args = parser.parse_args()
 
 with open(args.verilog, 'r') as f:
-    d = f.read()
-    # Remove newlines from module definitions, yosys started doing this as of
-    # commit ff8e999a7112 ("Split module ports, 20 per line")
-    fixed = multiline_module_re.sub(lambda m: m.group(0).replace("\n", ""), d)
+    strip_lpar = False
+    for line in f:
+        line = line.rstrip()
 
-    for line in fixed.splitlines():
         m = module_re.match(line)
         m2 = hookup_re.match(line)
         if m and m.group(1) in args.module:
-            module_name = m.group(1)
-            module_args = m.group(2)
-            print('module %s(' % (module_name))
-            print("")
-            print(header1.format(power=args.power, ground=args.ground))
-            print('  %s);' % module_args)
-            print(header2.format(power=args.power, ground=args.ground))
+            strip_lpar = True
+            print(line)
+            print('(')
+            print(header.format(power=args.power, ground=args.ground))
         elif m2 and m2.group(1) in args.module:
             print(line)
             print(header3.format(parent_power=args.parent_power, parent_ground=args.parent_ground, power=args.power, ground=args.ground))
+        elif strip_lpar:
+            print(line.replace('(', ' '))
+            strip_lpar = False
         else:
             print(line)
 

caravel/process-microwatt-verilog.sh

@@ -18,7 +18,7 @@ mv ${FILE_OUT}.tmp2 ${FILE_OUT}
 rm ${FILE_OUT}.tmp1
 
 # Add defines
-sed -i '1 a\
+sed -i '1 i\
 \
 /* JTAG */\
 `include "tap_top.v"\