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ECPIX-5: Add liteeth support

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Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This commit is contained in:
Paul Mackerras 2024-04-06 19:14:04 +11:00
parent 965b1cbcfe
commit 84ae593a09
6 changed files with 4446 additions and 2 deletions
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1
Makefile
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@ -228,6 +228,7 @@ OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
toplevel=fpga/top-ecpix5.vhdl
litedram_target=ecpix-5
soc_extra_v += litesdcard/generated/lattice.50e6/litesdcard_core.v
soc_extra_v += liteeth/generated/ecpix-5/liteeth_core.v
dmi_dtm=dmi_dtm_ecp5.vhdl
endif

37
constraints/ecpix-5.lpf
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@ -58,6 +58,43 @@ IOBUF PORT "spi_flash_wp_n" IO_TYPE=LVCMOS33;
LOCATE COMP "spi_flash_hold_n" SITE "AE1";
IOBUF PORT "spi_flash_hold_n" IO_TYPE=LVCMOS33;
// Ethernet
LOCATE COMP "rgmii_clocks_rx" SITE "E11";
LOCATE COMP "rgmii_clocks_tx" SITE "A12";
LOCATE COMP "rgmii_rst_n" SITE "C13";
LOCATE COMP "rgmii_int_n" SITE "B13";
LOCATE COMP "rgmii_mdc" SITE "C11";
LOCATE COMP "rgmii_mdio" SITE "A13";
LOCATE COMP "rgmii_rx_ctl" SITE "A11";
LOCATE COMP "rgmii_rx_data[0]" SITE "B11";
LOCATE COMP "rgmii_rx_data[1]" SITE "A10";
LOCATE COMP "rgmii_rx_data[2]" SITE "B10";
LOCATE COMP "rgmii_rx_data[3]" SITE "A9";
LOCATE COMP "rgmii_tx_ctl" SITE "C9";
LOCATE COMP "rgmii_tx_data[0]" SITE "D8";
LOCATE COMP "rgmii_tx_data[1]" SITE "C8";
LOCATE COMP "rgmii_tx_data[2]" SITE "B8";
LOCATE COMP "rgmii_tx_data[3]" SITE "A8";
IOBUF PORT "rgmii_clocks_rx" IO_TYPE=LVCMOS33;
IOBUF PORT "rgmii_clocks_tx" IO_TYPE=LVCMOS33;
IOBUF PORT "rgmii_rst_n" IO_TYPE=LVCMOS33;
IOBUF PORT "rgmii_int_n" IO_TYPE=LVCMOS33;
IOBUF PORT "rgmii_mdc" IO_TYPE=LVCMOS33;
IOBUF PORT "rgmii_mdio" IO_TYPE=LVCMOS33;
IOBUF PORT "rgmii_rx_ctl" IO_TYPE=LVCMOS33;
IOBUF PORT "rgmii_rx_data[0]" IO_TYPE=LVCMOS33 PULLMODE=UP;
IOBUF PORT "rgmii_rx_data[1]" IO_TYPE=LVCMOS33 PULLMODE=UP;
IOBUF PORT "rgmii_rx_data[2]" IO_TYPE=LVCMOS33 PULLMODE=UP;
IOBUF PORT "rgmii_rx_data[3]" IO_TYPE=LVCMOS33 PULLMODE=UP;
IOBUF PORT "rgmii_tx_ctl" IO_TYPE=LVCMOS33;
IOBUF PORT "rgmii_tx_data[0]" IO_TYPE=LVCMOS33;
IOBUF PORT "rgmii_tx_data[1]" IO_TYPE=LVCMOS33;
IOBUF PORT "rgmii_tx_data[2]" IO_TYPE=LVCMOS33;
IOBUF PORT "rgmii_tx_data[3]" IO_TYPE=LVCMOS33;
FREQUENCY PORT "eth_rx_clk" 125.0 MHz;
FREQUENCY PORT "eth_tx_clk" 125.0 MHz;
FREQUENCY PORT "rgmii_clocks_rx" 125.0 MHz;
// SD card slot and level translator
LOCATE COMP "sdcard_data[0]" SITE "N26";
LOCATE COMP "sdcard_data[1]" SITE "N25";

101
fpga/top-ecpix5.vhdl
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@ -23,6 +23,7 @@ entity toplevel is
LOG_LENGTH : natural := 0;
UART_IS_16550 : boolean := true;
HAS_UART1 : boolean := false;
USE_LITEETH : boolean := true;
USE_LITESDCARD : boolean := true;
ICACHE_NUM_LINES : natural := 64;
NGPIO : natural := 0
@ -57,6 +58,18 @@ entity toplevel is
spi_flash_wp_n : inout std_ulogic;
spi_flash_hold_n : inout std_ulogic;
-- Ethernet
rgmii_clocks_rx : in std_ulogic;
rgmii_clocks_tx : out std_ulogic;
rgmii_rst_n : out std_ulogic;
rgmii_int_n : in std_ulogic;
rgmii_mdc : out std_ulogic;
rgmii_mdio : inout std_ulogic;
rgmii_rx_ctl : in std_ulogic;
rgmii_rx_data : in std_ulogic_vector(3 downto 0);
rgmii_tx_ctl : out std_ulogic;
rgmii_tx_data : out std_ulogic_vector(3 downto 0);
-- SD card wires
sdcard_data : inout std_ulogic_vector(3 downto 0);
sdcard_cmd : inout std_ulogic;
@ -166,6 +179,7 @@ architecture behaviour of toplevel is
signal wb_ext_io_out : wb_io_slave_out;
signal wb_ext_is_dram_csr : std_ulogic;
signal wb_ext_is_dram_init : std_ulogic;
signal wb_ext_is_eth : std_ulogic;
signal wb_ext_is_sdcard : std_ulogic;
-- DRAM main data wishbone connection
@ -175,6 +189,10 @@ architecture behaviour of toplevel is
-- DRAM control wishbone connection
signal wb_dram_ctrl_out : wb_io_slave_out := wb_io_slave_out_init;
-- LiteEth connection
signal ext_irq_eth : std_ulogic;
signal wb_eth_out : wb_io_slave_out := wb_io_slave_out_init;
-- LiteSDCard connection
signal ext_irq_sdcard : std_ulogic := '0';
signal wb_sdcard_out : wb_io_slave_out := wb_io_slave_out_init;
@ -246,6 +264,7 @@ begin
LOG_LENGTH => LOG_LENGTH,
UART0_IS_16550 => UART_IS_16550,
HAS_UART1 => HAS_UART1,
HAS_LITEETH => USE_LITEETH,
HAS_SD_CARD => USE_LITESDCARD,
ICACHE_NUM_LINES => ICACHE_NUM_LINES,
NGPIO => NGPIO
@ -267,6 +286,7 @@ begin
spi_flash_sdat_i => spi_sdat_i,
-- External interrupts
ext_irq_eth => ext_irq_eth,
ext_irq_sdcard => ext_irq_sdcard,
-- DRAM wishbone
@ -278,6 +298,7 @@ begin
wb_ext_io_out => wb_ext_io_out,
wb_ext_is_dram_csr => wb_ext_is_dram_csr,
wb_ext_is_dram_init => wb_ext_is_dram_init,
wb_ext_is_eth => wb_ext_is_eth,
wb_ext_is_sdcard => wb_ext_is_sdcard,
-- DMA wishbone
@ -420,6 +441,83 @@ begin
led8_g_n <= not (dram_init_done and not dram_init_error);
end generate;
has_liteeth : if USE_LITEETH generate
component liteeth_core port (
sys_clock : in std_ulogic;
sys_reset : in std_ulogic;
rgmii_clocks_tx : out std_ulogic;
rgmii_clocks_rx : in std_ulogic;
rgmii_rst_n : out std_ulogic;
rgmii_int_n : in std_ulogic;
rgmii_mdio : inout std_ulogic;
rgmii_mdc : out std_ulogic;
rgmii_rx_ctl : in std_ulogic;
rgmii_rx_data : in std_ulogic_vector(3 downto 0);
rgmii_tx_ctl : out std_ulogic;
rgmii_tx_data : out std_ulogic_vector(3 downto 0);
wishbone_adr : in std_ulogic_vector(29 downto 0);
wishbone_dat_w : in std_ulogic_vector(31 downto 0);
wishbone_dat_r : out std_ulogic_vector(31 downto 0);
wishbone_sel : in std_ulogic_vector(3 downto 0);
wishbone_cyc : in std_ulogic;
wishbone_stb : in std_ulogic;
wishbone_ack : out std_ulogic;
wishbone_we : in std_ulogic;
wishbone_cti : in std_ulogic_vector(2 downto 0);
wishbone_bte : in std_ulogic_vector(1 downto 0);
wishbone_err : out std_ulogic;
interrupt : out std_ulogic
);
end component;
signal wb_eth_cyc : std_ulogic;
signal wb_eth_adr : std_ulogic_vector(29 downto 0);
begin
liteeth : liteeth_core
port map(
sys_clock => system_clk,
sys_reset => soc_rst,
rgmii_clocks_tx => rgmii_clocks_tx,
rgmii_clocks_rx => rgmii_clocks_rx,
rgmii_rst_n => rgmii_rst_n,
rgmii_int_n => rgmii_int_n,
rgmii_mdio => rgmii_mdio,
rgmii_mdc => rgmii_mdc,
rgmii_rx_ctl => rgmii_rx_ctl,
rgmii_rx_data => rgmii_rx_data,
rgmii_tx_ctl => rgmii_tx_ctl,
rgmii_tx_data => rgmii_tx_data,
wishbone_adr => wb_eth_adr,
wishbone_dat_w => wb_ext_io_in.dat,
wishbone_dat_r => wb_eth_out.dat,
wishbone_sel => wb_ext_io_in.sel,
wishbone_cyc => wb_eth_cyc,
wishbone_stb => wb_ext_io_in.stb,
wishbone_ack => wb_eth_out.ack,
wishbone_we => wb_ext_io_in.we,
wishbone_cti => "000",
wishbone_bte => "00",
wishbone_err => open,
interrupt => ext_irq_eth
);
-- Gate cyc with "chip select" from soc
wb_eth_cyc <= wb_ext_io_in.cyc and wb_ext_is_eth;
-- Remove top address bits as liteeth decoder doesn't know about them
wb_eth_adr <= x"000" & "000" & wb_ext_io_in.adr(14 downto 0);
-- LiteETH isn't pipelined
wb_eth_out.stall <= not wb_eth_out.ack;
end generate;
no_liteeth : if not USE_LITEETH generate
ext_irq_eth <= '0';
end generate;
-- SD card
-- The ECPIX-5 has a buffer/level translator chip in order to be able to
-- support 1.8V signalling to the SD card as well as 3V signalling.
@ -537,7 +635,8 @@ begin
end generate;
-- Mux WB response on the IO bus
wb_ext_io_out <= wb_sdcard_out when wb_ext_is_sdcard = '1' else
wb_ext_io_out <= wb_eth_out when wb_ext_is_eth = '1' else
wb_sdcard_out when wb_ext_is_sdcard = '1' else
wb_dram_ctrl_out;
led5_r_n <= '1';

18
liteeth/gen-src/ecpix-5.yml Normal file
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@ -0,0 +1,18 @@
# This file is derived from nexys_video.yml, which is:
# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
# PHY ----------------------------------------------------------------------
phy: LiteEthECP5PHYRGMII
vendor: lattice
# Core ---------------------------------------------------------------------
clk_freq: 125e6
core: wishbone
endianness: little
ntxslots: 2
nrxslots: 2
phy_rx_delay: 0
soc:
mem_map:
ethmac: 0x00010000

2
liteeth/gen-src/generate.sh
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@ -1,6 +1,6 @@
#!/bin/bash
TARGETS="arty nexys-video wukong-v2"
TARGETS="arty nexys-video wukong-v2 ecpix-5"
ME=$(realpath $0)
echo ME=$ME

4289
liteeth/generated/ecpix-5/liteeth_core.v Normal file
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