github.com/antonblanchard.microwatt
1
0
Fork 0
mirror of https://github.com/antonblanchard/microwatt.git synced 2026-01-11 23:43:15 +00:00
Code Releases Activity

verilator: Specify top level module

Browse Source 
While verilator finds the correct top level module with the current
setup, if we start adding simulation models it can get confused.

Explicitly specify the top level module.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This commit is contained in:
Anton Blanchard 2021-08-14 15:03:16 +10:00 committed by Anton Blanchard
parent 7e2de602ee
commit 8acd5a5607
2 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Makefile
View File

@ -205,7 +205,7 @@ microwatt.v: $(synth_files) $(RAM_INIT_FILE)
$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@" $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
$(VERILATOR) $(VERILATOR_FLAGS) -CFLAGS "$(VERILATOR_CFLAGS) -DCLK_FREQUENCY=$(CLK_FREQUENCY)" -Iuart16550 --assert --cc --exe --build $^ -o $@ $(VERILATOR) $(VERILATOR_FLAGS) -CFLAGS "$(VERILATOR_CFLAGS) -DCLK_FREQUENCY=$(CLK_FREQUENCY)" -Iuart16550 --assert --cc --exe --build $^ -o $@ -top-module toplevel
@cp -f obj_dir/microwatt-verilator microwatt-verilator @cp -f obj_dir/microwatt-verilator microwatt-verilator
microwatt_out.config: microwatt.json $(LPF) microwatt_out.config: microwatt.json $(LPF)

6
verilator/microwatt-verilator.cpp
View File

@ -1,5 +1,5 @@
#include <stdlib.h> #include <stdlib.h>
#include "Vmicrowatt.h" #include "Vtoplevel.h"
#include "verilated.h" #include "verilated.h"
#include "verilated_vcd_c.h" #include "verilated_vcd_c.h"
@ -24,7 +24,7 @@ double sc_time_stamp(void)
VerilatedVcdC *tfp; VerilatedVcdC *tfp;
#endif #endif
void tick(Vmicrowatt *top) void tick(Vtoplevel *top)
{ {
top->ext_clk = 1; top->ext_clk = 1;
top->eval(); top->eval();
@ -51,7 +51,7 @@ int main(int argc, char **argv)
Verilated::commandArgs(argc, argv); Verilated::commandArgs(argc, argv);
// init top verilog instance // init top verilog instance
Vmicrowatt* top = new Vmicrowatt; Vtoplevel* top = new Vtoplevel;
#if VM_TRACE #if VM_TRACE
// init trace dump // init trace dump