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ram: Rework main RAM interface

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This replaces the simple_ram_behavioural and mw_soc_memory modules
with a common wishbone_bram_wrapper.vhdl that interfaces the
pipelined WB with a lower-level RAM module, along with an FPGA
and a sim variants of the latter.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt
2019-10-23 12:08:55 +11:00
parent 9a63c098a5
commit 8e0389b973
21 changed files with 462 additions and 540 deletions
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2
scripts/run_test.sh
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@@ -21,7 +21,7 @@ Y=$(${MICROWATT_DIR}/scripts/hash.py tests/${TEST}.out)
cd $TMPDIR
cp ${MICROWATT_DIR}/tests/${TEST}.bin simple_ram_behavioural.bin
cp ${MICROWATT_DIR}/tests/${TEST}.bin main_ram.bin
X=$( ${MICROWATT_DIR}/core_tb | ${MICROWATT_DIR}/scripts/hash.py )