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ram: Rework main RAM interface

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This replaces the simple_ram_behavioural and mw_soc_memory modules
with a common wishbone_bram_wrapper.vhdl that interfaces the
pipelined WB with a lower-level RAM module, along with an FPGA
and a sim variants of the latter.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt
2019-10-23 12:08:55 +11:00
parent 9a63c098a5
commit 8e0389b973
21 changed files with 462 additions and 540 deletions
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2
scripts/test_micropython_long.py
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@@ -13,7 +13,7 @@ cwd = os.getcwd()
os.chdir(tempdir.name)
copyfile(os.path.join(cwd, 'tests/micropython.bin'),
os.path.join(tempdir.name, 'simple_ram_behavioural.bin'))
os.path.join(tempdir.name, 'main_ram.bin'))
cmd = [ os.path.join(cwd, './core_tb') ]