Merge pull request #133 from antonblanchard/ghdl-synth

Ghdl synth

common.vhdl

@@ -346,6 +346,7 @@ package body common is
        when SPR_XER =>
            n := 12;
        when others =>
+           n := 0;
            return "000000";
        end case;
        return "1" & std_ulogic_vector(to_unsigned(n, 5));

core.vhdl

@@ -143,6 +143,7 @@ begin
 
     icache_0: entity work.icache
         generic map(
+            SIM => SIM,
             LINE_SIZE => 64,
             NUM_LINES => 32,
 	    NUM_WAYS => 2

divider.vhdl

@@ -22,7 +22,6 @@ architecture behaviour of divider is
     signal result     : std_ulogic_vector(63 downto 0);
     signal sresult    : std_ulogic_vector(64 downto 0);
     signal oresult    : std_ulogic_vector(63 downto 0);
-    signal qbit       : std_ulogic;
     signal running    : std_ulogic;
     signal signcheck  : std_ulogic;
     signal count      : unsigned(6 downto 0);

execute1.vhdl

@@ -386,6 +386,7 @@ begin
 	            when "1110" => -- CROR
 			crresult := (e_in.cr(banum) or e_in.cr(bbnum));
 		    when others =>
+			crresult := '0';
 		        report "BAD CR?";
 	            end case;
 		    v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);

fpga/main_bram.vhdl

@@ -2,7 +2,6 @@
 
 library ieee;
 use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
 use ieee.numeric_std.all;
 use std.textio.all;
 
@@ -68,13 +67,13 @@ begin
 	    if we = '1' then
 		for i in 0 to 7 loop
 		    if sel(i) = '1' then
-			memory(conv_integer(addr))((i + 1) * 8 - 1 downto i * 8) <=
+			memory(to_integer(unsigned(addr)))((i + 1) * 8 - 1 downto i * 8) <=
 			    di((i + 1) * 8 - 1 downto i * 8);
 		    end if;
 		end loop;
 	    end if;
 	    if re = '1' then
-		obuf <= memory(conv_integer(addr));
+		obuf <= memory(to_integer(unsigned(addr)));
 	    end if;
 	    do <= obuf;
 	end if;

icache.vhdl

@@ -29,6 +29,7 @@ use work.wishbone_types.all;
 
 entity icache is
     generic (
+        SIM : boolean := false;
         -- Line size in bytes
         LINE_SIZE : positive := 64;
         -- Number of lines in a set
@@ -264,6 +265,7 @@ begin
     assert (64 = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
 	report "geometry bits don't add up" severity FAILURE;
 
+    sim_debug: if SIM generate
     debug: process
     begin
 	report "ROW_SIZE      = " & natural'image(ROW_SIZE);
@@ -280,6 +282,7 @@ begin
 	report "WAY_BITS      = " & natural'image(WAY_BITS);
 	wait;
     end process;
+    end generate;
 
     -- Generate a cache RAM for each way
     rams: for i in 0 to NUM_WAYS-1 generate

register_file.vhdl

@@ -92,4 +92,9 @@ begin
 	end process;
     end generate;
 
+    -- Keep GHDL synthesis happy
+    sim_dump_test_synth: if not SIM generate
+        sim_dump_done <= '0';
+    end generate;
+
 end architecture behaviour;

soc.vhdl

@@ -26,10 +26,7 @@ entity soc is
 
 	-- UART0 signals:
 	uart0_txd    : out std_ulogic;
-	uart0_rxd    : in  std_ulogic;
-
-	-- Misc (to use for things like LEDs)
-	core_terminated : out std_ulogic
+	uart0_rxd    : in  std_ulogic
 	);
 end entity soc;
 

writeback.vhdl

@@ -104,6 +104,7 @@ begin
         sign_extend <= '0';
         second_word <= '0';
 	xe := e_in.xerc;
+	data_in <= (others => '0');
 
         if e_in.write_enable = '1' then
             w_out.write_reg <= e_in.write_reg;