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Add core debug module

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This module adds some simple core controls:

  reset, stop, start, step

along with icache clear and reading the NIA and core
status bits

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org
This commit is contained in:
Benjamin Herrenschmidt
2019-09-10 17:43:52 +01:00
parent 554b753172
commit 98f0994698
10 changed files with 280 additions and 67 deletions
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7
fetch2.vhdl
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@@ -15,6 +15,7 @@ entity fetch2 is
stall_out : out std_ulogic;
flush_in : in std_ulogic;
stop_in : in std_ulogic;
i_in : in IcacheToFetch2Type;
i_out : out Fetch2ToIcacheType;
@@ -49,12 +50,12 @@ begin
v.valid := i_in.ack;
v.nia := f_in.nia;
v.insn := i_in.insn;
stall_out <= not i_in.ack;
stall_out <= stop_in or not i_in.ack;
if flush_in = '1' then
if flush_in = '1' or stop_in = '1' then
v.valid := '0';
end if;
v.stop_mark := stop_in;
-- Update registers
rin <= v;