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soc: Implement multiple CPU cores

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This adds an 'NCPUS' generic parameter to the soc module, which then
includes that many CPU cores.

The cores have separate addresses on the DMI interconnect, meaning
that external JTAG debug tools can view and control the state of each
core individually.

The syscon module has a new 'cpu_ctrl' register, where byte 0 contains
individual enable bits for each core, and byte 1 indicates the number
of cores.  If a core's enable bit is clear, the core is held in reset.
On system reset, the enable byte is set to 0x01, so only core 0 is
active.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This commit is contained in:
Paul Mackerras
2025-01-04 16:24:41 +11:00
parent 23ff954059
commit 9a06b0c182
3 changed files with 73 additions and 52 deletions
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3
include/microwatt_soc.h
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@@ -65,7 +65,8 @@
#define SYS_REG_UART_IS_16550 (1ull << 32)
#define SYS_REG_GIT_INFO 0x50
#define SYS_REG_GIT_IS_DIRTY (1ull << 63)
#define SYS_REG_CPU_CTRL 0x58
#define SYS_REG_CPU_CTRL_ENABLE 0xff
/*
* Register definitions for the potato UART