litedram: Add an L2 cache with store queue

This adds a cache between the wishbone and litedram with the following
features (at this point, it's still evolving)

  - 128 bytes line width in order to have a reasonable amount of
litedram pipelining on the 128-bit wide data port.

  - Configurable geometry otherwise

  - Stores are acked immediately on wishbone whether hit or miss
(minus a 2 cycles delay if there's a previous load response in the
way) and sent to LiteDRAM via 8 entries (configurable) store queue

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

Makefile

@@ -50,7 +50,7 @@ core_files = decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl \
 	loadstore1.vhdl mmu.vhdl dcache.vhdl writeback.vhdl core_debug.vhdl \
 	core.vhdl
 
-soc_files = wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl \
+soc_files = wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \
 	wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl
 
 soc_sim_files = sim_console.vhdl sim_uart.vhdl sim_bram_helpers.vhdl \

litedram/extras/wave.opt

@@ -0,0 +1,84 @@
+$ version 1.1
+
+# Signals in entities :
+/core_dram_tb/dram/rst
+/core_dram_tb/dram/system_clk
+/core_dram_tb/dram/system_reset
+/core_dram_tb/dram/wb_in
+/core_dram_tb/dram/wb_out
+/core_dram_tb/dram/user_port0_cmd_valid
+/core_dram_tb/dram/user_port0_cmd_ready
+/core_dram_tb/dram/user_port0_cmd_we
+/core_dram_tb/dram/user_port0_cmd_addr
+/core_dram_tb/dram/user_port0_wdata_valid
+/core_dram_tb/dram/user_port0_wdata_ready
+/core_dram_tb/dram/user_port0_wdata_we
+/core_dram_tb/dram/user_port0_wdata_data
+/core_dram_tb/dram/user_port0_rdata_valid
+/core_dram_tb/dram/user_port0_rdata_ready
+/core_dram_tb/dram/user_port0_rdata_data
+/core_dram_tb/dram/cache_tags
+/core_dram_tb/dram/cache_valids
+/core_dram_tb/dram/storeq_rd_ready
+/core_dram_tb/dram/storeq_rd_valid
+/core_dram_tb/dram/storeq_rd_data
+/core_dram_tb/dram/storeq_wr_ready
+/core_dram_tb/dram/storeq_wr_valid
+/core_dram_tb/dram/storeq_wr_data
+/core_dram_tb/dram/accept_store
+/core_dram_tb/dram/state
+/core_dram_tb/dram/wb_req
+/core_dram_tb/dram/store_queued
+/core_dram_tb/dram/read_ack_0
+/core_dram_tb/dram/read_ack_1
+/core_dram_tb/dram/read_ad3_0
+/core_dram_tb/dram/read_ad3_1
+/core_dram_tb/dram/read_way_0
+/core_dram_tb/dram/read_way_1
+/core_dram_tb/dram/req_index
+/core_dram_tb/dram/req_row
+/core_dram_tb/dram/req_hit_way
+/core_dram_tb/dram/req_tag
+/core_dram_tb/dram/req_op
+/core_dram_tb/dram/req_laddr
+/core_dram_tb/dram/req_ad3
+/core_dram_tb/dram/req_we
+/core_dram_tb/dram/req_wdata
+/core_dram_tb/dram/store_way
+/core_dram_tb/dram/store_index
+/core_dram_tb/dram/store_row
+/core_dram_tb/dram/cache_out
+/core_dram_tb/dram/plru_victim
+/core_dram_tb/dram/replace_way
+/core_dram_tb/dram/rams/do_read
+/core_dram_tb/dram/rams/do_write
+/core_dram_tb/dram/rams/rd_addr
+/core_dram_tb/dram/rams/wr_addr
+/core_dram_tb/dram/rams/wr_data
+/core_dram_tb/dram/rams/wr_sel
+/core_dram_tb/dram/rams/wr_sel_m
+/core_dram_tb/dram/rams/dout
+/core_dram_tb/dram/rams/way/clk
+/core_dram_tb/dram/rams/way/rd_en
+/core_dram_tb/dram/rams/way/rd_addr
+/core_dram_tb/dram/rams/way/rd_data
+/core_dram_tb/dram/rams/way/wr_sel
+/core_dram_tb/dram/rams/way/wr_addr
+/core_dram_tb/dram/rams/way/wr_data
+/core_dram_tb/dram/rams/way/rd_data0
+/core_dram_tb/dram/store_queue/wr_ready
+/core_dram_tb/dram/store_queue/wr_valid
+/core_dram_tb/dram/store_queue/wr_data
+/core_dram_tb/dram/store_queue/rd_ready
+/core_dram_tb/dram/store_queue/rd_valid
+/core_dram_tb/dram/store_queue/rd_data
+/core_dram_tb/dram/store_queue/rd_idx
+/core_dram_tb/dram/store_queue/rd_next
+/core_dram_tb/dram/store_queue/wr_idx
+/core_dram_tb/dram/store_queue/wr_next
+/core_dram_tb/dram/store_queue/op_prev
+/core_dram_tb/dram/store_queue/op_next
+/core_dram_tb/dram/store_queue/full
+/core_dram_tb/dram/store_queue/empty
+/core_dram_tb/dram/store_queue/push
+/core_dram_tb/dram/store_queue/pop

litedram/gen-src/sdram_init/include/system.h

@@ -9,9 +9,9 @@
 #define CONFIG_CPU_NOP		"nop"
 
 #ifdef __SIM__
-#define MEMTEST_BUS_SIZE	16
+#define MEMTEST_BUS_SIZE	512//16
-#define MEMTEST_DATA_SIZE	16
+#define MEMTEST_DATA_SIZE	1024//16
-#define MEMTEST_ADDR_SIZE	16
+#define MEMTEST_ADDR_SIZE	128//16
 #define CONFIG_SIM_DISABLE_DELAYS
 #endif
 

litedram/generated/arty/litedram_core.v

@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-26 20:37:38
+// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-30 20:25:53
 //--------------------------------------------------------------------------------
 module litedram_core(
 	input wire clk,

litedram/generated/nexys-video/litedram_core.v

@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-26 20:37:40
+// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-30 20:25:55
 //--------------------------------------------------------------------------------
 module litedram_core(
 	input wire clk,

litedram/generated/sim/litedram_core.init

@@ -510,7 +510,7 @@ a64b5a7d14004a39
 0000000000000000
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 0000000000000000
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@@ -519,11 +519,11 @@ f8c101a838800140
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@@ -531,67 +531,67 @@ f92101c0f90101b8
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@@ -605,138 +605,130 @@ ebe1fff881810008
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 0000000000000000
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@@ -756,22 +748,22 @@ f821ff713f804000
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@@ -780,27 +772,27 @@ f821ff713f804000
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@@ -874,7 +866,7 @@ f924000039290002
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@@ -908,7 +900,7 @@ fbfd00007fe9fa14
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@@ -924,7 +916,7 @@ f821ffb1480006e9
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@@ -1196,16 +1188,35 @@ e8010010ebc1fff0
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litedram/generated/sim/litedram_core.v

@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-26 20:37:42
+// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-30 20:25:57
 //--------------------------------------------------------------------------------
 module litedram_core(
 	input wire clk,

microwatt.core

@@ -48,6 +48,7 @@ filesets:
       - soc.vhdl
       - xics.vhdl
       - syscon.vhdl
+      - sync_fifo.vhdl
     file_type : vhdlSource-2008
 
   fpga:

sync_fifo.vhdl

@@ -0,0 +1,163 @@
+-- Synchronous FIFO with a protocol similar to AXI
+--
+-- The outputs are generated combinationally from the inputs
+-- in order to allow for back-to-back transfers with the type
+-- of flow control used by busses lite AXI, pipelined WB or
+-- LiteDRAM native port when the FIFO is full.
+--
+-- That means that care needs to be taken by the user not to
+-- generate the inputs combinationally from the outputs otherwise
+-- it would create a logic loop.
+--
+-- If breaking that loop is required, a stash buffer could be
+-- added to break the flow control "loop" between the read and
+-- the write port.
+--
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.utils.all;
+
+entity sync_fifo is
+    generic(
+        -- Fifo depth in entries
+        DEPTH     : natural := 64;
+
+        -- Fifo width in bits
+        WIDTH     : natural := 32;
+
+        -- When INIT_ZERO is set, the memory is pre-initialized to 0's
+        INIT_ZERO : boolean := false
+        );
+    port(
+        -- Control lines:
+        clk      : in std_ulogic;
+        reset    : in std_ulogic;
+
+        -- Write port
+        wr_ready : out std_ulogic;
+        wr_valid : in std_ulogic;
+        wr_data  : in std_ulogic_vector(WIDTH - 1 downto 0);
+
+        -- Read port
+        rd_ready : in std_ulogic;
+        rd_valid : out std_ulogic;
+        rd_data  : out std_ulogic_vector(WIDTH - 1 downto 0)
+        );
+end entity sync_fifo;
+
+architecture behaviour of sync_fifo is
+
+    subtype data_t is std_ulogic_vector(WIDTH - 1 downto 0);    
+    type memory_t is array(0 to DEPTH - 1) of data_t;
+
+    function init_mem return memory_t is
+        variable m : memory_t;
+    begin
+        if INIT_ZERO then
+            for i in 0 to DEPTH - 1 loop
+                m(i) := (others => '0');
+            end loop;
+        end if;
+        return m;
+    end function;
+
+    signal memory : memory_t := init_mem;
+
+    subtype index_t is integer range 0 to DEPTH - 1;
+    signal rd_idx  : index_t;
+    signal rd_next : index_t;
+    signal wr_idx  : index_t;
+    signal wr_next : index_t;
+
+    function next_index(idx : index_t) return index_t is
+        variable r : index_t;
+    begin
+        if ispow2(DEPTH) then
+            r := (idx + 1) mod DEPTH;
+        else
+            r := idx + 1;
+            if r = DEPTH then
+                r := 0;
+            end if;
+        end if;
+        return r;
+    end function;
+    
+    type op_t is (OP_POP, OP_PUSH);
+    signal op_prev : op_t := OP_POP;
+    signal op_next : op_t;
+
+    signal full, empty : std_ulogic;
+    signal push, pop   : std_ulogic;
+begin
+
+    -- Current state at last clock edge
+    empty <= '1' when rd_idx = wr_idx and op_prev = OP_POP  else '0';
+    full  <= '1' when rd_idx = wr_idx and op_prev = OP_PUSH else '0';
+
+    -- We can accept new data if we aren't full or we are but
+    -- the read port is going to accept data this cycle    
+    wr_ready <= rd_ready or not full;
+
+    -- We can provide data if we aren't empty or we are but
+    -- the write port is going to provide data this cycle
+    rd_valid <= wr_valid or not empty;
+
+    -- Internal control signals
+    push <= wr_ready and wr_valid;
+    pop  <= rd_ready and rd_valid;
+
+    -- Next state
+    rd_next <= next_index(rd_idx) when pop  = '1' else rd_idx;
+    wr_next <= next_index(wr_idx) when push = '1' else wr_idx;
+    with push & pop select op_next <=
+        OP_PUSH when "10",
+        OP_POP  when "01",
+        op_prev when others;
+
+    -- Read port output
+    rd_data <= memory(rd_idx) when empty = '0' else wr_data;
+
+    -- Read counter
+    reader: process(clk)
+    begin
+        if rising_edge(clk) then
+            if reset = '1' then
+                rd_idx <= 0;
+            else
+                rd_idx <= rd_next;
+            end if;
+        end if;
+    end process;
+
+    -- Write counter and memory write
+    producer: process(clk)
+    begin
+        if rising_edge(clk) then
+            if reset = '1' then
+                wr_idx <= 0;
+            else
+                wr_idx <= wr_next;
+
+                if push = '1' then
+                    memory(wr_idx) <= wr_data;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- Previous op latch used for generating empty/full
+    op: process(clk)
+    begin
+        if rising_edge(clk) then
+            if reset = '1' then
+                op_prev <= OP_POP;
+            else
+                op_prev <= op_next;
+            end if;
+        end if;
+    end process;
+
+end architecture behaviour;