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Merge pull request #60 from antonblanchard/testbenches
Add a few more test benches
This commit is contained in:
Anton Blanchard
GitHub
commit
a4c8dd860a
9
Makefile
9
Makefile
@ -2,7 +2,7 @@ GHDL=ghdl
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GHDLFLAGS=--std=08
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CFLAGS=-O2 -Wall
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all = core_tb simple_ram_behavioural_tb soc_reset_tb
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all = core_tb simple_ram_behavioural_tb soc_reset_tb icache_tb multiply_tb
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# XXX
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# loadstore_tb fetch_tb
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@ -27,6 +27,7 @@ glibc_random_helpers.o:
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glibc_random.o: glibc_random_helpers.o
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helpers.o:
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icache.o: common.o wishbone_types.o
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icache_tb.o: common.o wishbone_types.o icache.o simple_ram_behavioural.o
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insn_helpers.o:
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loadstore1.o: common.o
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loadstore2.o: common.o helpers.o wishbone_types.o
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@ -54,9 +55,15 @@ core_tb: core_tb.o simple_ram_behavioural_helpers_c.o sim_console_c.o
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fetch_tb: fetch_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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icache_tb: icache_tb.o
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$(GHDL) -e $(GHDLFLAGS) -Wl,simple_ram_behavioural_helpers_c.o $@
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loadstore_tb: loadstore_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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multiply_tb: multiply_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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simple_ram_tb: simple_ram_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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120
icache_tb.vhdl
Normal file
120
icache_tb.vhdl
Normal file
@ -0,0 +1,120 @@
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library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.common.all;
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use work.wishbone_types.all;
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entity icache_tb is
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end icache_tb;
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architecture behave of icache_tb is
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signal clk : std_ulogic;
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signal rst : std_ulogic;
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signal i_out : Fetch2ToIcacheType;
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signal i_in : IcacheToFetch2Type;
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signal wb_bram_in : wishbone_master_out;
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signal wb_bram_out : wishbone_slave_out;
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constant clk_period : time := 10 ns;
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begin
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icache0: entity work.icache
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generic map(
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LINE_SIZE_DW => 8,
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NUM_LINES => 4
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)
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port map(
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clk => clk,
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rst => rst,
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i_in => i_out,
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i_out => i_in,
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wishbone_out => wb_bram_in,
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wishbone_in => wb_bram_out
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);
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-- BRAM Memory slave
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bram0: entity work.mw_soc_memory
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generic map(
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MEMORY_SIZE => 128,
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RAM_INIT_FILE => "icache_test.bin"
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)
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port map(
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clk => clk,
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rst => rst,
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wishbone_in => wb_bram_in,
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wishbone_out => wb_bram_out
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);
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clk_process: process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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rst_process: process
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begin
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rst <= '1';
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wait for 2*clk_period;
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rst <= '0';
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wait;
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end process;
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stim: process
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begin
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i_out.req <= '0';
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i_out.addr <= (others => '0');
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wait for 4*clk_period;
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i_out.req <= '1';
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i_out.addr <= x"0000000000000004";
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wait for 30*clk_period;
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assert i_in.ack = '1';
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assert i_in.insn = x"00000001";
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i_out.req <= '0';
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wait for clk_period;
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-- hit
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i_out.req <= '1';
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i_out.addr <= x"0000000000000008";
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wait for clk_period/2;
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assert i_in.ack = '1';
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assert i_in.insn = x"00000002";
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wait for clk_period/2;
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-- another miss
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i_out.req <= '1';
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i_out.addr <= x"0000000000000040";
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wait for 30*clk_period;
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assert i_in.ack = '1';
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assert i_in.insn = x"00000010";
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-- test something that aliases
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i_out.req <= '1';
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i_out.addr <= x"0000000000000100";
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wait for clk_period/2;
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assert i_in.ack = '0';
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wait for clk_period/2;
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wait for 30*clk_period;
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assert i_in.ack = '1';
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assert i_in.insn = x"00000040";
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i_out.req <= '0';
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assert false report "end of test" severity failure;
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wait;
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end process;
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end;
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@ -3,6 +3,7 @@ use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.decode_types.all;
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use work.common.all;
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use work.glibc_random.all;
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use work.ppc_fx_insns.all;
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@ -14,9 +15,9 @@ architecture behave of multiply_tb is
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signal clk : std_ulogic;
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constant clk_period : time := 10 ns;
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constant pipeline_depth: integer := 6;
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constant pipeline_depth: integer := 4;
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signal m1 : DecodeToMultiplyType;
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signal m1 : Decode2ToMultiplyType;
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signal m2 : MultiplyToWritebackType;
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begin
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multiply_0: entity work.multiply
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@ -38,8 +39,7 @@ begin
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wait for clk_period;
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m1.valid <= '1';
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m1.mul_type <= LOWER_64;
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m1.nia <= (others => '0');
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m1.insn_type <= OP_MUL_L64;
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m1.write_reg <= "10001";
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m1.data1 <= '0' & x"0000000000001000";
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m1.data2 <= '0' & x"0000000000001111";
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@ -58,9 +58,9 @@ begin
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wait for clk_period;
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assert m2.valid = '1';
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assert m2.write_enable = '1';
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assert m2.write_reg = "10001";
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assert m2.write_data = x"0000000001111000";
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assert m2.write_reg_enable = '1';
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assert m2.write_reg_nr = "10001";
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assert m2.write_reg_data = x"0000000001111000";
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assert m2.write_cr_enable = '0';
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wait for clk_period;
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@ -76,11 +76,11 @@ begin
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wait for clk_period * (pipeline_depth-1);
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assert m2.valid = '1';
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assert m2.write_enable = '1';
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assert m2.write_reg = "10001";
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assert m2.write_data = x"0000000001111000";
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assert m2.write_reg_enable = '1';
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assert m2.write_reg_nr = "10001";
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assert m2.write_reg_data = x"0000000001111000";
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assert m2.write_cr_enable = '1';
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assert m2.cr = x"4";
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assert m2.write_cr_data = x"40000000";
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-- test mulld
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mulld_loop : for i in 0 to 1000 loop
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@ -92,7 +92,7 @@ begin
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m1.data1 <= '0' & ra;
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m1.data2 <= '0' & rb;
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m1.valid <= '1';
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m1.mul_type <= LOWER_64;
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m1.insn_type <= OP_MUL_L64;
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wait for clk_period;
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@ -102,8 +102,8 @@ begin
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assert m2.valid = '1';
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assert to_hstring(behave_rt) = to_hstring(m2.write_data)
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report "bad mulld expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_data);
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assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
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report "bad mulld expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
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end loop;
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-- test mulhdu
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@ -116,7 +116,7 @@ begin
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m1.data1 <= '0' & ra;
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m1.data2 <= '0' & rb;
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m1.valid <= '1';
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m1.mul_type <= UPPER_64;
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m1.insn_type <= OP_MUL_H64;
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wait for clk_period;
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@ -126,8 +126,8 @@ begin
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assert m2.valid = '1';
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assert to_hstring(behave_rt) = to_hstring(m2.write_data)
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report "bad mulhdu expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_data);
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assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
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report "bad mulhdu expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
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end loop;
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-- test mulhd
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@ -140,7 +140,7 @@ begin
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m1.data1 <= ra(63) & ra;
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m1.data2 <= rb(63) & rb;
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m1.valid <= '1';
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m1.mul_type <= UPPER_64;
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m1.insn_type <= OP_MUL_H64;
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wait for clk_period;
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@ -150,8 +150,8 @@ begin
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assert m2.valid = '1';
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assert to_hstring(behave_rt) = to_hstring(m2.write_data)
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report "bad mulhd expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_data);
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assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
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report "bad mulhd expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
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end loop;
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-- test mullw
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@ -166,7 +166,7 @@ begin
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m1.data2 <= (others => rb(31));
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m1.data2(31 downto 0) <= rb(31 downto 0);
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m1.valid <= '1';
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m1.mul_type <= LOWER_64;
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m1.insn_type <= OP_MUL_L64;
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wait for clk_period;
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@ -176,8 +176,8 @@ begin
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assert m2.valid = '1';
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assert to_hstring(behave_rt) = to_hstring(m2.write_data)
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report "bad mullw expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_data);
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assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
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report "bad mullw expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
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end loop;
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-- test mulhw
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@ -192,7 +192,7 @@ begin
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m1.data2 <= (others => rb(31));
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m1.data2(31 downto 0) <= rb(31 downto 0);
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m1.valid <= '1';
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m1.mul_type <= UPPER_32;
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m1.insn_type <= OP_MUL_H32;
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wait for clk_period;
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@ -202,8 +202,8 @@ begin
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assert m2.valid = '1';
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assert to_hstring(behave_rt) = to_hstring(m2.write_data)
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report "bad mulhw expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_data);
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assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
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report "bad mulhw expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
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end loop;
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-- test mulhwu
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@ -218,7 +218,7 @@ begin
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m1.data2 <= (others => '0');
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m1.data2(31 downto 0) <= rb(31 downto 0);
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m1.valid <= '1';
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m1.mul_type <= UPPER_32;
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m1.insn_type <= OP_MUL_H32;
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wait for clk_period;
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@ -228,8 +228,8 @@ begin
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assert m2.valid = '1';
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assert to_hstring(behave_rt) = to_hstring(m2.write_data)
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report "bad mulhwu expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_data);
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assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
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report "bad mulhwu expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
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end loop;
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-- test mulli
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@ -243,7 +243,7 @@ begin
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m1.data2 <= (others => si(15));
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m1.data2(15 downto 0) <= si;
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m1.valid <= '1';
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m1.mul_type <= LOWER_64;
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m1.insn_type <= OP_MUL_L64;
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wait for clk_period;
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@ -253,8 +253,8 @@ begin
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assert m2.valid = '1';
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assert to_hstring(behave_rt) = to_hstring(m2.write_data)
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report "bad mulli expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_data);
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assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
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report "bad mulli expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
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end loop;
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assert false report "end of test" severity failure;
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