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Remove some FPGA style signal inits

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These don't work on the ASIC flow, so remove them and initialise
them explicitly where required.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This commit is contained in:
Anton Blanchard 2022-06-07 17:38:24 +10:00 committed by Anton Blanchard
parent f5e06c2d4b
commit a750365ffa
6 changed files with 30 additions and 27 deletions
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6
control.vhdl
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@ -64,8 +64,8 @@ architecture rtl of control is
signal r_int, rin_int : reg_internal_type := reg_internal_init; signal r_int, rin_int : reg_internal_type := reg_internal_init;
signal gpr_write_valid : std_ulogic := '0'; signal gpr_write_valid : std_ulogic;
signal cr_write_valid : std_ulogic := '0'; signal cr_write_valid : std_ulogic;
type tag_register is record type tag_register is record
wr_gpr : std_ulogic; wr_gpr : std_ulogic;
@ -245,6 +245,8 @@ begin
end if; end if;
if rst = '1' then if rst = '1' then
gpr_write_valid <= '0';
cr_write_valid <= '0';
v_int := reg_internal_init; v_int := reg_internal_init;
valid_tmp := '0'; valid_tmp := '0';
end if; end if;

22
core.vhdl
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@ -121,17 +121,17 @@ architecture behave of core is
signal do_interrupt: std_ulogic; signal do_interrupt: std_ulogic;
-- Delayed/Latched resets and alt_reset -- Delayed/Latched resets and alt_reset
signal rst_fetch1 : std_ulogic := '1'; signal rst_fetch1 : std_ulogic;
signal rst_fetch2 : std_ulogic := '1'; signal rst_fetch2 : std_ulogic;
signal rst_icache : std_ulogic := '1'; signal rst_icache : std_ulogic;
signal rst_dcache : std_ulogic := '1'; signal rst_dcache : std_ulogic;
signal rst_dec1 : std_ulogic := '1'; signal rst_dec1 : std_ulogic;
signal rst_dec2 : std_ulogic := '1'; signal rst_dec2 : std_ulogic;
signal rst_ex1 : std_ulogic := '1'; signal rst_ex1 : std_ulogic;
signal rst_fpu : std_ulogic := '1'; signal rst_fpu : std_ulogic;
signal rst_ls1 : std_ulogic := '1'; signal rst_ls1 : std_ulogic;
signal rst_wback : std_ulogic := '1'; signal rst_wback : std_ulogic;
signal rst_dbg : std_ulogic := '1'; signal rst_dbg : std_ulogic;
signal alt_reset_d : std_ulogic; signal alt_reset_d : std_ulogic;
signal sim_cr_dump: std_ulogic; signal sim_cr_dump: std_ulogic;

5
execute1.vhdl
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@ -99,8 +99,8 @@ architecture behaviour of execute1 is
signal mshort_p : std_ulogic_vector(31 downto 0) := (others => '0'); signal mshort_p : std_ulogic_vector(31 downto 0) := (others => '0');
signal valid_in : std_ulogic; signal valid_in : std_ulogic;
signal ctrl: ctrl_t := (others => (others => '0')); signal ctrl: ctrl_t;
signal ctrl_tmp: ctrl_t := (others => (others => '0')); signal ctrl_tmp: ctrl_t;
signal right_shift, rot_clear_left, rot_clear_right: std_ulogic; signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
signal rot_sign_ext: std_ulogic; signal rot_sign_ext: std_ulogic;
signal rotator_result: std_ulogic_vector(63 downto 0); signal rotator_result: std_ulogic_vector(63 downto 0);
@ -406,6 +406,7 @@ begin
r <= reg_type_init; r <= reg_type_init;
ctrl.tb <= (others => '0'); ctrl.tb <= (others => '0');
ctrl.dec <= (others => '0'); ctrl.dec <= (others => '0');
ctrl.cfar <= (others => '0');
ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0'); ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
else else
r <= rin; r <= rin;

4
gpio.vhdl
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@ -40,8 +40,8 @@ architecture behaviour of gpio is
constant GPIO_REG_DATA_CLR : std_ulogic_vector(GPIO_REG_BITS-1 downto 0) := "00101"; constant GPIO_REG_DATA_CLR : std_ulogic_vector(GPIO_REG_BITS-1 downto 0) := "00101";
-- Current output value and direction -- Current output value and direction
signal reg_data : std_ulogic_vector(NGPIO - 1 downto 0) := (others => '0'); signal reg_data : std_ulogic_vector(NGPIO - 1 downto 0);
signal reg_dirn : std_ulogic_vector(NGPIO - 1 downto 0) := (others => '0'); signal reg_dirn : std_ulogic_vector(NGPIO - 1 downto 0);
signal reg_in1 : std_ulogic_vector(NGPIO - 1 downto 0); signal reg_in1 : std_ulogic_vector(NGPIO - 1 downto 0);
signal reg_in2 : std_ulogic_vector(NGPIO - 1 downto 0); signal reg_in2 : std_ulogic_vector(NGPIO - 1 downto 0);

18
soc.vhdl
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@ -223,15 +223,15 @@ architecture behaviour of soc is
signal dmi_core_ack : std_ulogic; signal dmi_core_ack : std_ulogic;
-- Delayed/latched resets and alt_reset -- Delayed/latched resets and alt_reset
signal rst_core : std_ulogic := '1'; signal rst_core : std_ulogic;
signal rst_uart : std_ulogic := '1'; signal rst_uart : std_ulogic;
signal rst_xics : std_ulogic := '1'; signal rst_xics : std_ulogic;
signal rst_spi : std_ulogic := '1'; signal rst_spi : std_ulogic;
signal rst_gpio : std_ulogic := '1'; signal rst_gpio : std_ulogic;
signal rst_bram : std_ulogic := '1'; signal rst_bram : std_ulogic;
signal rst_dtm : std_ulogic := '1'; signal rst_dtm : std_ulogic;
signal rst_wbar : std_ulogic := '1'; signal rst_wbar : std_ulogic;
signal rst_wbdb : std_ulogic := '1'; signal rst_wbdb : std_ulogic;
signal alt_reset_d : std_ulogic; signal alt_reset_d : std_ulogic;
-- IO branch split: -- IO branch split:

2
spi_flash_ctrl.vhdl
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@ -50,7 +50,7 @@ architecture rtl of spi_flash_ctrl is
constant SPI_REG_INVALID : std_ulogic_vector(SPI_REG_BITS-1 downto 0) := "111"; constant SPI_REG_INVALID : std_ulogic_vector(SPI_REG_BITS-1 downto 0) := "111";
-- Control register -- Control register
signal ctrl_reg : std_ulogic_vector(15 downto 0) := (others => '0'); signal ctrl_reg : std_ulogic_vector(15 downto 0);
alias ctrl_reset : std_ulogic is ctrl_reg(0); alias ctrl_reset : std_ulogic is ctrl_reg(0);
alias ctrl_cs : std_ulogic is ctrl_reg(1); alias ctrl_cs : std_ulogic is ctrl_reg(1);
alias ctrl_rsrv1 : std_ulogic is ctrl_reg(2); alias ctrl_rsrv1 : std_ulogic is ctrl_reg(2);