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Wishbone debug module

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This adds a debug module off the DMI (debug) bus which can act as a
wishbone master to generate read and write cycles.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt
2019-09-10 17:31:25 +01:00
parent ee52fd4d80
commit b46f81fae4
6 changed files with 268 additions and 16 deletions
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45
scripts/mw_debug.py
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@@ -54,8 +54,49 @@ def main():
urc.set_instruction("USER2")
urc.shift_ir()
print("Reading 0x00: %x" % do_read(urc, 0))
print("Reading 0xaa: %x" % do_read(urc, 0xaa))
print("Reading memory at 0:")
do_write(urc, 0, 0)
do_write(urc, 2, 0x7ff)
print("00: %016x" % do_read(urc, 1))
print("08: %016x" % do_read(urc, 1))
print("10: %016x" % do_read(urc, 1))
print("18: %016x" % do_read(urc, 1))
do_write(urc, 0, 0x10)
do_write(urc, 1, 0xabcdef0123456789)
do_write(urc, 0, 0)
do_write(urc, 2, 0x7ff)
print("00: %016x" % do_read(urc, 1))
print("08: %016x" % do_read(urc, 1))
print("10: %016x" % do_read(urc, 1))
print("18: %016x" % do_read(urc, 1))
# urc.set_dr_in(0,73,0);
# print("Test DR_IN 1:", urc.get_dr_in_string())
# urc.set_dr_in(0xa,3,0);
# print("Test DR_IN 2:", urc.get_dr_in_string())
# urc.set_dr_in(0x5,7,4);
# print("Test DR_IN 3:", urc.get_dr_in_string())
# urc.set_dr_in(1,73,73);
# print("Test DR_IN 4:", urc.get_dr_in_string())
# print("Reading ADDR reg: %x" % do_read(urc, 0))
# print("Writing all 1's to it:")
# do_write(urc, 0, 0xffffffffffffffff)
# print("Reading ADDR reg: %x" % do_read(urc, 0))
# print("Writing 0xabcdef0123456789 to it:")
# do_write(urc, 0, 0xabcdef0123456789)
# print("Reading ADDR reg: %x" % do_read(urc, 0))
# urc.set_dr_in(0x1,41,0)
# print("Sending:", urc.get_dr_in_string())
# urc.shift_dr()
# urc.set_dr_in(0x0,41,0)
# urc.shift_dr()
# print("Got1:", urc.get_dr_out_string())
# urc.shift_dr()
# print("Got2:", hex(urc.get_dr_out()))
if __name__ == "__main__":