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wishbone_bram_wrapper ram_addr_bits is 1 bit off

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log2ceil() returns the number of bits required to store a value, so we
need to pass in memory_size-1, not memory_size.

Every other user of log2ceil() gets this right.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This commit is contained in:
Anton Blanchard 2022-03-17 18:03:29 +11:00 committed by Anton Blanchard
parent 30fd936c12
commit b5accb78b2
1 changed files with 1 additions and 1 deletions
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wishbone_bram_wrapper.vhdl
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@ -24,7 +24,7 @@ entity wishbone_bram_wrapper is
end entity wishbone_bram_wrapper; end entity wishbone_bram_wrapper;
architecture behaviour of wishbone_bram_wrapper is architecture behaviour of wishbone_bram_wrapper is
constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE) - 3; constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE-1) - 3;
-- RAM interface -- RAM interface
signal ram_addr : std_logic_vector(ram_addr_bits - 1 downto 0); signal ram_addr : std_logic_vector(ram_addr_bits - 1 downto 0);